diff c476bb76e5163d7105679b52569a50806bd95349 uncommitted
--- a/sys/src/cmd/7c/7.out.h
+++ b/sys/src/cmd/7c/7.out.h
@@ -425,7 +425,13 @@
 	ASHA256H2,
 	ASHA256SU0,
 	ASHA256SU1,
-	
+
+	ALDP,
+	ALDPW,
+	ALDPWU,
+	AFLDPS,
+	AFLDPD,
+
 	ALAST,
 };
 
--- a/sys/src/cmd/7c/gc.h
+++ b/sys/src/cmd/7c/gc.h
@@ -46,6 +46,7 @@
 struct	Prog
 {
 	Adr	from;
+	Adr	from3;		/* third argument */
 	Adr	to;
 	Prog*	link;
 	long	lineno;
--- a/sys/src/cmd/7c/list.c
+++ b/sys/src/cmd/7c/list.c
@@ -42,25 +42,30 @@
 int
 Pconv(Fmt *fp)
 {
-	char str[STRINGSZ];
+	char str[STRINGSZ], *s, *e;
 	Prog *p;
 	int a;
 
 	p = va_arg(fp->args, Prog*);
 	a = p->as;
+	s = str;
+	e = str+sizeof(str);
+
+	s = seprint(s, e, "	%A	%D", a, &p->from);
 	if(a == ADATA)
-		snprint(str, sizeof(str), "	%A	%D/%d,%D", a, &p->from, p->reg, &p->to);
-	else
-	if(p->as == ATEXT)
-		snprint(str, sizeof(str), "	%A	%D,%d,%D", a, &p->from, p->reg, &p->to);
-	else
-	if(p->reg == NREG)
-		snprint(str, sizeof(str), "	%A	%D,%D", a, &p->from, &p->to);
-	else
-	if(p->from.type != D_FREG)
-		snprint(str, sizeof(str), "	%A	%D,R%d,%D", a, &p->from, p->reg, &p->to);
-	else
-		snprint(str, sizeof(str), "	%A	%D,F%d,%D", a, &p->from, p->reg, &p->to);
+		seprint(s, e, "/%d,%D", p->reg, &p->to);
+	else if(p->as == ATEXT)
+		seprint(s, e, ",%d,%D", p->reg, &p->to);
+	else{
+		if(p->reg == NREG)
+			s = seprint(s, e, ",%D", &p->to);
+		else if(p->from.type != D_FREG)
+			s = seprint(s, e, ",R%d,%D", p->reg, &p->to);
+		else
+			s = seprint(s, e, ",F%d,%D", p->reg, &p->to);
+		if(p->from3.type != D_NONE)
+			seprint(s, e, ",%D", &p->from3);
+	}
 	return fmtstrcpy(fp, str);
 }
 
--- a/sys/src/cmd/7c/peep.c
+++ b/sys/src/cmd/7c/peep.c
@@ -105,7 +105,9 @@
 {
 	Reg *r, *r1, *r2;
 	Prog *p, *p1;
+	long odt;
 	int t;
+
 /*
  * complete R structure
  */
@@ -136,6 +138,7 @@
 		case ANAME:
 		case ASIGNAME:
 			p = p->link;
+			break;
 		}
 	}
 
@@ -213,6 +216,88 @@
 	}
 	if(t)
 		goto loop1;
+
+	for(r=firstr; r!=R; r=r->link){
+		p = r->prog;
+		switch(p->as){
+		default:
+			continue;
+		case AMOVW:
+		case AFMOVS:
+		case AMOV:
+		case AFMOVD:
+			break;
+		}
+		r1 = r->link;
+		if(r1 == R)
+			continue;
+		p1 = r1->prog;
+		if(p1->as != p->as)
+			continue;
+
+		/* (f)mov o1(Rx), Rn; (f)mov o2(Rx), Rm */
+		if(p->from.type == D_OREG && p1->from.type == D_OREG &&
+		   p->from.reg == p1->from.reg && p->to.reg != p1->to.reg &&
+		   (p->to.type == D_REG && p1->to.type == D_REG ||
+		    p->to.type == D_FREG && p1->to.type == D_FREG))
+		if(p->from.reg != NREG || p->from.sym == p1->from.sym){
+			if(p->from.offset == p1->from.offset){
+				/*
+				 * (f)mov o(Rx), Rn
+				 * (f)mov o(Rx), Rm
+				 *
+				 * (f)mov o(Rx), Rn
+				 * (f)mov Rn, Rm
+				 */
+				print("o(Rx),Rn; Rn,Rm\n	%P\n	%P\n", p, p1);
+				p1->from = p->to;
+				continue;
+			}
+
+			if(p->from.reg == NREG) /* FIXME - this needs to work in 7l as well */
+				continue;
+			if((odt = p1->from.offset - p->from.offset) < 0)
+				odt = -odt;
+			if(odt == 4){
+				if(p->from.offset & 3)
+					continue;
+				if(!((p->from.offset >= -256 && p->from.offset <= 252) ||
+					 (p1->from.offset >= -256 && p1->from.offset <= 252)))
+					continue;
+				switch(p->as){
+				default:
+					continue;
+				case AMOVW:	p->as = ALDPW; break;
+				case AMOVWU:	p->as = ALDPWU; break;
+				case AFMOVS:	p->as = AFLDPS; break;
+				}
+			}else if(odt == 8){
+				if(p->from.offset & 7)
+					continue;
+				if(!((p->from.offset >= -512 && p->from.offset <= 504) ||
+					 (p1->from.offset >= -512 && p1->from.offset <= 504)))
+					continue;
+				switch(p->as){
+				default:
+					continue;
+				case AMOV:	p->as = ALDP; break;
+				case AFMOVD:	p->as = AFLDPD; break;
+				}
+			}else
+				continue;
+
+			if(p1->from.offset > p->from.offset){
+				p->from3 = p1->to;
+			}else{
+				p->from3 = p->to;
+				p->from = p1->from;
+				p->to = p1->to;
+			}
+			print("	%P\n", p);
+			excise(r1);
+		}
+	}
+
 	/*
 	 * look for MOVB x,R; MOVB R,R
 	 */
@@ -368,6 +453,7 @@
 	p->as = ANOP;
 	p->scond = zprog.scond;
 	p->from = zprog.from;
+	p->from3 = zprog.from3;
 	p->to = zprog.to;
 	p->reg = zprog.reg; /**/
 }
@@ -1069,7 +1155,6 @@
 int
 copyu(Prog *p, Adr *v, Adr *s)
 {
-
 	switch(p->as) {
 
 	default:
--- a/sys/src/cmd/7c/sgen.c
+++ b/sys/src/cmd/7c/sgen.c
@@ -3,7 +3,6 @@
 void
 noretval(int n)
 {
-
 	if(n & 1) {
 		gins(ANOP, Z, Z);
 		p->to.type = D_REG;
--- a/sys/src/cmd/7c/swt.c
+++ b/sys/src/cmd/7c/swt.c
@@ -309,6 +309,8 @@
 	bf[0] = p->as;
 	bf[1] = p->as>>8;
 	bf[2] = p->reg;
+	if(p->from3.type != D_NONE)
+		bf[2] |= 0x40;
 	l = p->lineno;
 	bf[3] = l;
 	bf[4] = l>>8;
@@ -315,6 +317,8 @@
 	bf[5] = l>>16;
 	bf[6] = l>>24;
 	bp = zaddr(bf+7, &p->from, sf);
+	if(bf[2] & 0x40)
+		bp = zaddr(bp, &p->from3, 0);
 	bp = zaddr(bp, &p->to, st);
 	Bwrite(b, bf, bp-bf);
 }
--- a/sys/src/cmd/7c/txt.c
+++ b/sys/src/cmd/7c/txt.c
@@ -40,6 +40,7 @@
 	zprog.from.type = D_NONE;
 	zprog.from.name = D_NONE;
 	zprog.from.reg = NREG;
+	zprog.from3 = zprog.from;
 	zprog.to = zprog.from;
 
 	regnode.op = OREGISTER;
--- a/sys/src/cmd/7l/asmout.c
+++ b/sys/src/cmd/7l/asmout.c
@@ -57,6 +57,8 @@
 static long	omovlit(int, Prog*, Adr*, int);
 static int	movesize(int);
 static long	oaddi(long, long, int, int);
+static long	oldp(long, long, int, int, int);
+static long	opldp(int);
 
 /*
  * valid pstate field values, and value to use in instruction
@@ -351,6 +353,13 @@
 		}
 		break;
 
+	case 49:	/* ldpw(u) */
+		v = regoff(&p->from);
+		s = movesize(o->as);
+		r = p->from.reg;
+		o1 = oldp(opldp(p->as), v>>s, r, p->to.reg, p->from3.reg);
+		break;
+
 	case 22:	/* movT (R)O!,R; movT O(R)!, R -> ldrT */
 		v = p->from.offset;
 		if(v < -256 || v > 255)
@@ -1507,6 +1516,16 @@
 }
 
 static long
+oldp(long o, long v, int f, int t, int t2)
+{
+	o |= (v&0x7F)<<15;
+	o |= t2 << 10;
+	o |= f << 5;
+	o |= t;
+	return o;
+}
+
+static long
 opldr12(int a)
 {
 	switch(a){
@@ -1525,6 +1544,18 @@
 }
 
 static long
+opldp(int a)
+{
+	switch(a){
+	case ALDP:	return 2<<30 | 5<<27 | 2<<23 | 1<<2; /* imm7<<15 | Rt2<<10 | Rn<<5 | Rt */
+	case ALDPW:	return 1<<30 | 5<<27 | 2<<23 | 1<<22;
+	case ALDPWU:	return 0<<30 | 5<<27 | 2<<23 | 1<<2;
+	}
+	diag("bad opldp %A\n%P", a, curp);
+	return 0;
+}
+
+static long
 opstr12(int a)
 {
 	return LD2STR(opldr12(a));
@@ -1704,9 +1735,12 @@
 {
 	switch(a){
 	case AMOV:
+	case ALDP:
 		return 3;
 	case AMOVW:
 	case AMOVWU:
+	case ALDPW:
+	case ALDPWU:
 		return 2;
 	case AMOVH:
 	case AMOVHU:
@@ -1715,8 +1749,10 @@
 	case AMOVBU:
 		return 0;
 	case AFMOVS:
+	case AFLDPS:
 		return 2;
 	case AFMOVD:
+	case AFLDPD:
 		return 3;
 	default:
 		return -1;
--- a/sys/src/cmd/7l/l.h
+++ b/sys/src/cmd/7l/l.h
@@ -105,6 +105,7 @@
 	char	a1;
 	char	a2;
 	char	a3;
+	char	a4;
 	char	type;
 	char	size;
 	char	param;
--- a/sys/src/cmd/7l/optab.c
+++ b/sys/src/cmd/7l/optab.c
@@ -2,431 +2,476 @@
 
 Optab	optab[] =
 {
-	{ ATEXT,	C_LEXT,	C_NONE,	C_LCON, 	 0, 0, 0 },
-	{ ATEXT,	C_LEXT,	C_REG,	C_LCON, 	 0, 0, 0 },
-	{ ATEXT,	C_ADDR,	C_NONE,	C_LCON, 	 0, 0, 0 },
-	{ ATEXT,	C_ADDR,	C_REG,	C_LCON, 	 0, 0, 0 },
+	{ ATEXT,	C_LEXT,	C_NONE,	C_LCON,	C_NONE, 	 0, 0, 0 },
+	{ ATEXT,	C_LEXT,	C_REG,	C_LCON,	C_NONE, 	 0, 0, 0 },
+	{ ATEXT,	C_ADDR,	C_NONE,	C_LCON,	C_NONE, 	 0, 0, 0 },
+	{ ATEXT,	C_ADDR,	C_REG,	C_LCON,	C_NONE, 	 0, 0, 0 },
 
 	/* arithmetic operations */
-	{ AADD,		C_REG,	C_REG,	C_REG,		 1, 4, 0 },
-	{ AADD,		C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
-	{ AADC,		C_REG,	C_REG,	C_REG,		 1, 4, 0 },
-	{ AADC,		C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
-	{ ANEG,		C_REG,	C_NONE,	C_REG,		25, 4, 0 },
-	{ ANGC,		C_REG,	C_NONE,	C_REG,		17, 4, 0 },
-	{ ACMP,		C_REG,	C_RSP,	C_NONE,		 1, 4, 0 },
+	{ AADD,		C_REG,	C_REG,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ AADD,		C_REG,	C_NONE,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ AADC,		C_REG,	C_REG,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ AADC,		C_REG,	C_NONE,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ ANEG,		C_REG,	C_NONE,	C_REG,	C_NONE,		25, 4, 0 },
+	{ ANGC,		C_REG,	C_NONE,	C_REG,	C_NONE,		17, 4, 0 },
+	{ ACMP,		C_REG,	C_RSP,	C_NONE,	C_NONE,		 1, 4, 0 },
 
-	{ AADD,		C_ADDCON,	C_RSP,	C_RSP,		 2, 4, 0 },
-	{ AADD,		C_ADDCON,	C_NONE,	C_RSP,		 2, 4, 0 },
-	{ ACMP,		C_ADDCON,	C_RSP,	C_NONE,		 2, 4, 0 },
+	{ AADD,		C_ADDCON,	C_RSP,	C_RSP,	C_NONE,		 2, 4, 0 },
+	{ AADD,		C_ADDCON,	C_NONE,	C_RSP,	C_NONE,		 2, 4, 0 },
+	{ ACMP,		C_ADDCON,	C_RSP,	C_NONE,	C_NONE,		 2, 4, 0 },
 
-	{ AADD,		C_LCON,	C_REG,	C_REG,		13, 8, 0,	LFROM },
-	{ AADD,		C_LCON,	C_NONE,	C_REG,		13, 8, 0,	LFROM },
-	{ ACMP,		C_LCON,	C_REG,	C_NONE,		13, 8, 0,	LFROM },
+	{ AADD,		C_LCON,	C_REG,	C_REG,	C_NONE,		13, 8, 0,	LFROM },
+	{ AADD,		C_LCON,	C_NONE,	C_REG,	C_NONE,		13, 8, 0,	LFROM },
+	{ ACMP,		C_LCON,	C_REG,	C_NONE,	C_NONE,		13, 8, 0,	LFROM },
 
-	{ AADD,		C_SHIFT,C_REG,	C_REG,		 3, 4, 0 },
-	{ AADD,		C_SHIFT,C_NONE,	C_REG,		 3, 4, 0 },
-	{ AMVN,		C_SHIFT,C_NONE,	C_REG,		 3, 4, 0 },
-	{ ACMP,		C_SHIFT,C_REG,	C_NONE,		 3, 4, 0 },
-	{ ANEG,		C_SHIFT,C_NONE,	C_REG,		26, 4, 0 },
+	{ AADD,		C_SHIFT,C_REG,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ AADD,		C_SHIFT,C_NONE,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ AMVN,		C_SHIFT,C_NONE,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ ACMP,		C_SHIFT,C_REG,	C_NONE,	C_NONE,		 3, 4, 0 },
+	{ ANEG,		C_SHIFT,C_NONE,	C_REG,	C_NONE,		26, 4, 0 },
 
-	{ AADD,		C_REG,	C_RSP,	C_RSP,		27, 4, 0 },
-	{ AADD,		C_REG,	C_NONE,	C_RSP,		27, 4, 0 },
-	{ AADD,		C_EXTREG,C_RSP,	C_RSP,		27, 4, 0 },
-	{ AADD,		C_EXTREG,C_NONE,	C_RSP,		27, 4, 0 },
-	{ AMVN,		C_EXTREG,C_NONE,	C_RSP,		27, 4, 0 },
-	{ ACMP,		C_EXTREG,C_RSP,	C_NONE,		27, 4, 0 },
+	{ AADD,		C_REG,	C_RSP,	C_RSP,	C_NONE,		27, 4, 0 },
+	{ AADD,		C_REG,	C_NONE,	C_RSP,	C_NONE,		27, 4, 0 },
+	{ AADD,		C_EXTREG,C_RSP,	C_RSP,	C_NONE,		27, 4, 0 },
+	{ AADD,		C_EXTREG,C_NONE,	C_RSP,	C_NONE,		27, 4, 0 },
+	{ AMVN,		C_EXTREG,C_NONE,	C_RSP,	C_NONE,		27, 4, 0 },
+	{ ACMP,		C_EXTREG,C_RSP,	C_NONE,	C_NONE,		27, 4, 0 },
 
-	{ AADD,		C_REG,	C_REG,	C_REG,		 1, 4, 0 },
-	{ AADD,		C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
+	{ AADD,		C_REG,	C_REG,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ AADD,		C_REG,	C_NONE,	C_REG,	C_NONE,		 1, 4, 0 },
 
 	/* logical operations */
-	{ AAND,		C_REG,	C_REG,	C_REG,		 1, 4, 0 },
-	{ AANDW,	C_REG,	C_REG,	C_REG,		 1, 4, 0 },
-	{ AAND,		C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
-	{ AANDW,	C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
-	{ ABIC,		C_REG,	C_REG,	C_REG,		 1, 4, 0 },
-	{ ABICW,	C_REG,	C_REG,	C_REG,		 1, 4, 0 },
-	{ ABIC,		C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
-	{ ABICW,	C_REG,	C_NONE,	C_REG,		 1, 4, 0 },
+	{ AAND,		C_REG,	C_REG,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ AANDW,	C_REG,	C_REG,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ AAND,		C_REG,	C_NONE,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ AANDW,	C_REG,	C_NONE,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ ABIC,		C_REG,	C_REG,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ ABICW,	C_REG,	C_REG,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ ABIC,		C_REG,	C_NONE,	C_REG,	C_NONE,		 1, 4, 0 },
+	{ ABICW,	C_REG,	C_NONE,	C_REG,	C_NONE,		 1, 4, 0 },
 
-	{ AAND,		C_BITCON64,C_REG,C_REG,		53, 4, 0 },
-	{ AANDW,	C_BITCON32,C_REG,C_REG,		53, 4, 0 },
-	{ AAND,		C_BITCON64,C_NONE,C_REG,	53, 4, 0 },
-	{ AANDW,	C_BITCON32,C_NONE,C_REG,	53, 4, 0 },
+	{ AAND,		C_BITCON64,C_REG,C_REG,	C_NONE,		53, 4, 0 },
+	{ AANDW,	C_BITCON32,C_REG,C_REG,	C_NONE,		53, 4, 0 },
+	{ AAND,		C_BITCON64,C_NONE,C_REG,	C_NONE,	53, 4, 0 },
+	{ AANDW,	C_BITCON32,C_NONE,C_REG,	C_NONE,	53, 4, 0 },
 
-	{ AAND,		C_LCON,	C_REG,	C_REG,		28, 8, 0,	LFROM },
-	{ AANDW,	C_LCON,	C_REG,	C_REG,		28, 8, 0,	LFROM },
-	{ AAND,		C_LCON,	C_NONE,	C_REG,		28, 8, 0,	LFROM },
-	{ AANDW,	C_LCON,	C_NONE,	C_REG,		28, 8, 0,	LFROM },
-	{ ABIC,		C_LCON,	C_REG,	C_REG,		28, 8, 0,	LFROM },
-	{ ABICW,	C_LCON,	C_REG,	C_REG,		28, 8, 0,	LFROM },
-	{ ABIC,		C_LCON,	C_NONE,	C_REG,		28, 8, 0,	LFROM },
-	{ ABICW,	C_LCON,	C_NONE,	C_REG,		28, 8, 0,	LFROM },
+	{ AAND,		C_LCON,	C_REG,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
+	{ AANDW,	C_LCON,	C_REG,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
+	{ AAND,		C_LCON,	C_NONE,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
+	{ AANDW,	C_LCON,	C_NONE,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
+	{ ABIC,		C_LCON,	C_REG,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
+	{ ABICW,	C_LCON,	C_REG,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
+	{ ABIC,		C_LCON,	C_NONE,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
+	{ ABICW,	C_LCON,	C_NONE,	C_REG,	C_NONE,		28, 8, 0,	LFROM },
 
-	{ AAND,		C_SHIFT,C_REG,	C_REG,		 3, 4, 0 },
-	{ AANDW,	C_SHIFT,C_REG,	C_REG,		 3, 4, 0 },
-	{ AAND,		C_SHIFT,C_NONE,	C_REG,		 3, 4, 0 },
-	{ AANDW,	C_SHIFT,C_NONE,	C_REG,		 3, 4, 0 },
-	{ ABIC,		C_SHIFT,C_REG,	C_REG,		 3, 4, 0 },
-	{ ABICW,	C_SHIFT,C_REG,	C_REG,		 3, 4, 0 },
-	{ ABIC,		C_SHIFT,C_NONE,	C_REG,		 3, 4, 0 },
-	{ ABICW,	C_SHIFT,C_NONE,	C_REG,		 3, 4, 0 },
+	{ AAND,		C_SHIFT,C_REG,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ AANDW,	C_SHIFT,C_REG,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ AAND,		C_SHIFT,C_NONE,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ AANDW,	C_SHIFT,C_NONE,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ ABIC,		C_SHIFT,C_REG,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ ABICW,	C_SHIFT,C_REG,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ ABIC,		C_SHIFT,C_NONE,	C_REG,	C_NONE,		 3, 4, 0 },
+	{ ABICW,	C_SHIFT,C_NONE,	C_REG,	C_NONE,		 3, 4, 0 },
 
 	/* moves */
-	{ AMOV,		C_RSP,	C_NONE,	C_RSP,		24, 4, 0 },
-	{ AMVN,		C_REG,	C_NONE,	C_REG,		24, 4, 0 },
-	{ AMOVB,		C_REG,	C_NONE,	C_REG,		45, 4, 0 },
-	{ AMOVBU,	C_REG,	C_NONE,	C_REG,		45, 4, 0 },
-	{ AMOVH,		C_REG,	C_NONE,	C_REG,		45, 4, 0 },	/* also MOVHU */
-	{ AMOVW,		C_REG,	C_NONE,	C_REG,		45, 4, 0 },	/* also MOVWU */
+	{ AMOV,		C_RSP,	C_NONE,	C_RSP,	C_NONE,		24, 4, 0 },
+	{ AMVN,		C_REG,	C_NONE,	C_REG,	C_NONE,		24, 4, 0 },
+	{ AMOVB,		C_REG,	C_NONE,	C_REG,	C_NONE,		45, 4, 0 },
+	{ AMOVBU,	C_REG,	C_NONE,	C_REG,	C_NONE,		45, 4, 0 },
+	{ AMOVH,		C_REG,	C_NONE,	C_REG,	C_NONE,		45, 4, 0 },	/* also MOVHU */
+	{ AMOVW,		C_REG,	C_NONE,	C_REG,	C_NONE,		45, 4, 0 },	/* also MOVWU */
 	/* TO DO: MVN C_SHIFT */
 
 	/* MOVs that become MOVK/MOVN/MOVZ/ADD/SUB/OR */
-	{ AMOVW,	C_MOVCON,	C_NONE,	C_REG,		32, 4, 0 },
-	{ AMOV,		C_MOVCON,	C_NONE,	C_REG,		32, 4, 0 },
-//	{ AMOVW,	C_ADDCON,	C_NONE,	C_REG,		2, 4, 0 },
-//	{ AMOV,		C_ADDCON,	C_NONE,	C_REG,		2, 4, 0 },
+	{ AMOVW,	C_MOVCON,	C_NONE,	C_REG,	C_NONE,		32, 4, 0 },
+	{ AMOV,		C_MOVCON,	C_NONE,	C_REG,	C_NONE,		32, 4, 0 },
+//	{ AMOVW,	C_ADDCON,	C_NONE,	C_REG,	C_NONE,		2, 4, 0 },
+//	{ AMOV,		C_ADDCON,	C_NONE,	C_REG,	C_NONE,		2, 4, 0 },
 
-	{ AMOV,		C_BITCON64,	C_NONE,	C_REG,		53, 4, 0 },
-	{ AMOVW,	C_BITCON32,	C_NONE,	C_REG,		53, 4, 0 },
+	{ AMOV,		C_BITCON64,	C_NONE,	C_REG,	C_NONE,		53, 4, 0 },
+	{ AMOVW,	C_BITCON32,	C_NONE,	C_REG,	C_NONE,		53, 4, 0 },
 
-	{ AMOVK,		C_LCON,	C_NONE,	C_REG,			33, 4, 0 },
+	{ AMOVK,		C_LCON,	C_NONE,	C_REG,	C_NONE,			33, 4, 0 },
 
-	{ AMOV,	C_AECON,C_NONE,	C_REG,		 4, 4, REGSB },
-	{ AMOV,	C_AACON,C_NONE,	C_REG,		 4, 4, REGSP },
+	{ AMOV,	C_AECON,C_NONE,	C_REG,	C_NONE,		 4, 4, REGSB },
+	{ AMOV,	C_AACON,C_NONE,	C_REG,	C_NONE,		 4, 4, REGSP },
 
-	{ ASDIV,	C_REG,	C_NONE,	C_REG,		1, 4, 0 },
-	{ ASDIV,	C_REG,	C_REG,	C_REG,		1, 4, 0 },
+	{ ASDIV,	C_REG,	C_NONE,	C_REG,	C_NONE,		1, 4, 0 },
+	{ ASDIV,	C_REG,	C_REG,	C_REG,	C_NONE,		1, 4, 0 },
 
-	{ AB,		C_NONE,	C_NONE,	C_SBRA,		 5, 4, 0 },
-	{ ABL,	C_NONE,	C_NONE,	C_SBRA,		 5, 4, 0 },
+	{ AB,		C_NONE,	C_NONE,	C_SBRA,	C_NONE,		 5, 4, 0 },
+	{ ABL,	C_NONE,	C_NONE,	C_SBRA,	C_NONE,		 5, 4, 0 },
 
-	{ AB,		C_NONE,	C_NONE,	C_ZOREG,	 	6, 4, 0 },
-	{ ABL,	C_NONE,	C_NONE,	C_ZOREG,	 	6, 4, 0 },
-	{ ARET,	C_NONE,	C_NONE,	C_REG,		6, 4, 0 },
-	{ ARET,	C_NONE, C_NONE, C_ZOREG,		6, 4, 0 },
+	{ AB,		C_NONE,	C_NONE,	C_ZOREG,	C_NONE,	 	6, 4, 0 },
+	{ ABL,	C_NONE,	C_NONE,	C_ZOREG,	C_NONE,	 	6, 4, 0 },
+	{ ARET,	C_NONE,	C_NONE,	C_REG,	C_NONE,		6, 4, 0 },
+	{ ARET,	C_NONE, C_NONE, C_ZOREG,	C_NONE,		6, 4, 0 },
 
-	{ AADRP,	C_SBRA,	C_NONE,	C_REG,		60, 4, 0 },
-	{ AADR,	C_SBRA,	C_NONE,	C_REG,		61, 4, 0 },
+	{ AADRP,	C_SBRA,	C_NONE,	C_REG,	C_NONE,		60, 4, 0 },
+	{ AADR,	C_SBRA,	C_NONE,	C_REG,	C_NONE,		61, 4, 0 },
 
-	{ ABFM,	C_LCON, C_REG, C_REG,		42, 4, 0 },
-	{ ABFI,	C_LCON, C_REG, C_REG,		43, 4, 0 },
+	{ ABFM,	C_LCON, C_REG, C_REG,	C_NONE,		42, 4, 0 },
+	{ ABFI,	C_LCON, C_REG, C_REG,	C_NONE,		43, 4, 0 },
 
-	{ AEXTR,	C_LCON, C_REG, C_REG,		44, 4, 0 },
-	{ ASXTB,	C_REG,	C_NONE,	C_REG,	45, 4, 0 },
-	{ ACLS,	C_REG,	C_NONE,	C_REG,	46, 4, 0 },
+	{ AEXTR,	C_LCON, C_REG, C_REG,	C_NONE,		44, 4, 0 },
+	{ ASXTB,	C_REG,	C_NONE,	C_REG,	C_NONE,	45, 4, 0 },
+	{ ACLS,	C_REG,	C_NONE,	C_REG,	C_NONE,	46, 4, 0 },
 
-	{ ABEQ,	C_NONE,	C_NONE,	C_SBRA,		 7, 4, 0 },
+	{ ABEQ,	C_NONE,	C_NONE,	C_SBRA,	C_NONE,		 7, 4, 0 },
 
-	{ ALSL,		C_LCON,	C_REG,	C_REG,		 8, 4, 0 },
-	{ ALSL,		C_LCON,	C_NONE,	C_REG,		 8, 4, 0 },
+	{ ALSL,		C_LCON,	C_REG,	C_REG,	C_NONE,		 8, 4, 0 },
+	{ ALSL,		C_LCON,	C_NONE,	C_REG,	C_NONE,		 8, 4, 0 },
 
-	{ ALSL,		C_REG,	C_NONE,	C_REG,		 9, 4, 0 },
-	{ ALSL,		C_REG,	C_REG,	C_REG,		 9, 4, 0 },
+	{ ALSL,		C_REG,	C_NONE,	C_REG,	C_NONE,		 9, 4, 0 },
+	{ ALSL,		C_REG,	C_REG,	C_REG,	C_NONE,		 9, 4, 0 },
 
-	{ ASVC,		C_NONE,	C_NONE,	C_LCON,		10, 4, 0 },
-	{ ASVC,		C_NONE,	C_NONE,	C_NONE,		10, 4, 0 },
+	{ ASVC,		C_NONE,	C_NONE,	C_LCON,	C_NONE,		10, 4, 0 },
+	{ ASVC,		C_NONE,	C_NONE,	C_NONE,	C_NONE,		10, 4, 0 },
 
-	{ ADWORD,	C_NONE,	C_NONE,	C_VCON,		11, 8, 0 },
-	{ ADWORD,	C_NONE,	C_NONE,	C_LEXT,		11, 8, 0 },
-	{ ADWORD,	C_NONE,	C_NONE,	C_ADDR,		11, 8, 0 },
+	{ ADWORD,	C_NONE,	C_NONE,	C_VCON,	C_NONE,		11, 8, 0 },
+	{ ADWORD,	C_NONE,	C_NONE,	C_LEXT,	C_NONE,		11, 8, 0 },
+	{ ADWORD,	C_NONE,	C_NONE,	C_ADDR,	C_NONE,		11, 8, 0 },
 
-	{ AWORD,	C_NONE,	C_NONE,	C_LCON,		14, 4, 0 },
-	{ AWORD,	C_NONE,	C_NONE,	C_LEXT,		14, 4, 0 },
-	{ AWORD,	C_NONE,	C_NONE,	C_ADDR,		14, 4, 0 },
+	{ AWORD,	C_NONE,	C_NONE,	C_LCON,	C_NONE,		14, 4, 0 },
+	{ AWORD,	C_NONE,	C_NONE,	C_LEXT,	C_NONE,		14, 4, 0 },
+	{ AWORD,	C_NONE,	C_NONE,	C_ADDR,	C_NONE,		14, 4, 0 },
 
-	{ AMOVW,	C_LCON,	C_NONE,	C_REG,		12, 4, 0,	LFROM },
-	{ AMOV,		C_LCON,	C_NONE,	C_REG,		12, 4, 0,	LFROM },
 
-	{ AMOVW,	C_REG,	C_NONE,	C_ADDR,		64, 8, 0,	LTO },
-	{ AMOVB,	C_REG,	C_NONE,	C_ADDR,		64, 8, 0,	LTO },
-	{ AMOVBU,	C_REG,	C_NONE,	C_ADDR,		64, 8, 0,	LTO },
-	{ AMOVW,	C_ADDR,	C_NONE,	C_REG,		65, 8, 0,	LFROM },
-	{ AMOVBU,	C_ADDR,	C_NONE,	C_REG,		65, 8, 0,	LFROM },
+	{ AMOVW,	C_LCON,	C_NONE,	C_REG,	C_NONE,		12, 4, 0,	LFROM },
+	{ AMOV,		C_LCON,	C_NONE,	C_REG,	C_NONE,		12, 4, 0,	LFROM },
 
-	{ AMUL,		C_REG,	C_REG,	C_REG,		15, 4, 0 },
-	{ AMUL,		C_REG,	C_NONE,	C_REG,		15, 4, 0 },
-	{ AMADD,		C_REG,	C_REG,	C_REG,		15, 4, 0 },
+	{ AMOVW,	C_REG,	C_NONE,	C_ADDR,	C_NONE,		64, 8, 0,	LTO },
+	{ AMOVB,	C_REG,	C_NONE,	C_ADDR,	C_NONE,		64, 8, 0,	LTO },
+	{ AMOVBU,	C_REG,	C_NONE,	C_ADDR,	C_NONE,		64, 8, 0,	LTO },
+	{ AMOVW,	C_ADDR,	C_NONE,	C_REG,	C_NONE,		65, 8, 0,	LFROM },
+	{ AMOVBU,	C_ADDR,	C_NONE,	C_REG,	C_NONE,		65, 8, 0,	LFROM },
 
-	{ AREM,		C_REG,	C_REG,	C_REG,		16, 8, 0 },
-	{ AREM,		C_REG,	C_NONE,	C_REG,		16, 8, 0 },
+	{ AMUL,		C_REG,	C_REG,	C_REG,	C_NONE,		15, 4, 0 },
+	{ AMUL,		C_REG,	C_NONE,	C_REG,	C_NONE,		15, 4, 0 },
+	{ AMADD,		C_REG,	C_REG,	C_REG,	C_NONE,		15, 4, 0 },
 
-	{ ACSEL,		C_COND,	C_REG,	C_REG,		18, 4, 0 },	/* from3 optional */
-	{ ACSET,		C_COND,	C_NONE,	C_REG,		18, 4, 0 },
+	{ AREM,		C_REG,	C_REG,	C_REG,	C_NONE,		16, 8, 0 },
+	{ AREM,		C_REG,	C_NONE,	C_REG,	C_NONE,		16, 8, 0 },
 
-	{ ACCMN,		C_COND,	C_REG,	C_LCON,		19, 4, 0 },	/* from3 either C_REG or C_LCON */
+	{ ACSEL,		C_COND,	C_REG,	C_REG,	C_NONE,		18, 4, 0 },	/* from3 optional */
+	{ ACSET,		C_COND,	C_NONE,	C_REG,	C_NONE,		18, 4, 0 },
 
+	{ ACCMN,		C_COND,	C_REG,	C_LCON,	C_NONE,		19, 4, 0 },	/* from3 either C_REG or C_LCON */
+
 	/* scaled 12-bit unsigned displacement store */
 
-	{ AMOVB,	C_REG,	C_NONE,	C_SEXT1,		20, 4, REGSB },  // 
-	{ AMOVB,	C_REG,	C_NONE,	C_UAUTO4K,	20, 4, REGSP },  // 
-	{ AMOVB,	C_REG,	C_NONE,	C_UOREG4K,		20, 4, 0 },  // 
-	{ AMOVBU,	C_REG,	C_NONE,	C_SEXT1,		20, 4, REGSB },  // 
-	{ AMOVBU,	C_REG,	C_NONE,	C_UAUTO4K,	20, 4, REGSP },  // 
-	{ AMOVBU,	C_REG,	C_NONE,	C_UOREG4K,		20, 4, 0 },  // 
+	{ AMOVB,	C_REG,	C_NONE,	C_SEXT1,	C_NONE,		20, 4, REGSB },  // 
+	{ AMOVB,	C_REG,	C_NONE,	C_UAUTO4K,	C_NONE,	20, 4, REGSP },  // 
+	{ AMOVB,	C_REG,	C_NONE,	C_UOREG4K,	C_NONE,		20, 4, 0 },  // 
+	{ AMOVBU,	C_REG,	C_NONE,	C_SEXT1,	C_NONE,		20, 4, REGSB },  // 
+	{ AMOVBU,	C_REG,	C_NONE,	C_UAUTO4K,	C_NONE,	20, 4, REGSP },  // 
+	{ AMOVBU,	C_REG,	C_NONE,	C_UOREG4K,	C_NONE,		20, 4, 0 },  // 
 
-	{ AMOVH,	C_REG,	C_NONE,	C_SEXT2,		20, 4, REGSB },  //
-	{ AMOVH,	C_REG,	C_NONE,	C_UAUTO8K,	20,	4, REGSP },	//
-	{ AMOVH,	C_REG,	C_NONE,	C_ZOREG,		20, 4, 0 },  // 
-	{ AMOVH,	C_REG,	C_NONE,	C_UOREG8K,	20,	4, 0 },	//
+	{ AMOVH,	C_REG,	C_NONE,	C_SEXT2,	C_NONE,		20, 4, REGSB },  //
+	{ AMOVH,	C_REG,	C_NONE,	C_UAUTO8K,	C_NONE,	20,	4, REGSP },	//
+	{ AMOVH,	C_REG,	C_NONE,	C_ZOREG,	C_NONE,		20, 4, 0 },  // 
+	{ AMOVH,	C_REG,	C_NONE,	C_UOREG8K,	C_NONE,	20,	4, 0 },	//
 
-	{ AMOVW,	C_REG,	C_NONE,	C_SEXT4,		20, 4, REGSB },  //
-	{ AMOVW,	C_REG,	C_NONE,	C_UAUTO16K,	20,	4, REGSP },	//
-	{ AMOVW,	C_REG,	C_NONE,	C_ZOREG,		20, 4, 0 },  // 
-	{ AMOVW,	C_REG,	C_NONE,	C_UOREG16K,	20,	4, 0 },	//
+	{ AMOVW,	C_REG,	C_NONE,	C_SEXT4,	C_NONE,		20, 4, REGSB },  //
+	{ AMOVW,	C_REG,	C_NONE,	C_UAUTO16K,	C_NONE,	20,	4, REGSP },	//
+	{ AMOVW,	C_REG,	C_NONE,	C_ZOREG,	C_NONE,		20, 4, 0 },  // 
+	{ AMOVW,	C_REG,	C_NONE,	C_UOREG16K,	C_NONE,	20,	4, 0 },	//
 
 	/* unscaled 9-bit signed displacement store */
-	{ AMOVB,	C_REG,	C_NONE,	C_NSAUTO,	20, 4, REGSP },  // 
-	{ AMOVB,	C_REG,	C_NONE,	C_NSOREG,	20, 4, 0 },  // 
-	{ AMOVBU,	C_REG,	C_NONE,	C_NSAUTO,	20, 4, REGSP },  // 
-	{ AMOVBU,	C_REG,	C_NONE,	C_NSOREG,	20, 4, 0 },  // 
+	{ AMOVB,	C_REG,	C_NONE,	C_NSAUTO,	C_NONE,	20, 4, REGSP },  // 
+	{ AMOVB,	C_REG,	C_NONE,	C_NSOREG,	C_NONE,	20, 4, 0 },  // 
+	{ AMOVBU,	C_REG,	C_NONE,	C_NSAUTO,	C_NONE,	20, 4, REGSP },  // 
+	{ AMOVBU,	C_REG,	C_NONE,	C_NSOREG,	C_NONE,	20, 4, 0 },  // 
 
-	{ AMOVH,	C_REG,	C_NONE,	C_NSAUTO,	20,	4, REGSP },	//
-	{ AMOVH,	C_REG,	C_NONE,	C_NSOREG,	20,	4, 0 },	//
-	{ AMOVW,	C_REG,	C_NONE,	C_NSAUTO,	20,	4, REGSP },	//
-	{ AMOVW,	C_REG,	C_NONE,	C_NSOREG,	20,	4, 0 },	//
+	{ AMOVH,	C_REG,	C_NONE,	C_NSAUTO,	C_NONE,	20,	4, REGSP },	//
+	{ AMOVH,	C_REG,	C_NONE,	C_NSOREG,	C_NONE,	20,	4, 0 },	//
+	{ AMOVW,	C_REG,	C_NONE,	C_NSAUTO,	C_NONE,	20,	4, REGSP },	//
+	{ AMOVW,	C_REG,	C_NONE,	C_NSOREG,	C_NONE,	20,	4, 0 },	//
 
-	{ AMOV,	C_REG,	C_NONE,	C_SEXT8,		20, 4, REGSB },
-	{ AMOV,	C_REG,	C_NONE,	C_UAUTO32K,	20,	4, REGSP },
-	{ AMOV,	C_REG,	C_NONE,	C_ZOREG,		20, 4, 0 },
-	{ AMOV,	C_REG,	C_NONE,	C_UOREG32K,	20,	4, 0 },
+	{ AMOV,	C_REG,	C_NONE,	C_SEXT8,	C_NONE,		20, 4, REGSB },
+	{ AMOV,	C_REG,	C_NONE,	C_UAUTO32K,	C_NONE,	20,	4, REGSP },
+	{ AMOV,	C_REG,	C_NONE,	C_ZOREG,	C_NONE,		20, 4, 0 },
+	{ AMOV,	C_REG,	C_NONE,	C_UOREG32K,	C_NONE,	20,	4, 0 },
 
-	{ AMOV,	C_REG,	C_NONE,	C_NSOREG,	20,	4, 0 },	//
-	{ AMOV,	C_REG,	C_NONE,	C_NSAUTO,	20,	4, REGSP },	//
+	{ AMOV,	C_REG,	C_NONE,	C_NSOREG,	C_NONE,	20,	4, 0 },	//
+	{ AMOV,	C_REG,	C_NONE,	C_NSAUTO,	C_NONE,	20,	4, REGSP },	//
 
 	/* short displacement load */
 
-	{ AMOVB,	C_SEXT1,	C_NONE,	C_REG,		21, 4, REGSB },  // 
-	{ AMOVB,	C_UAUTO4K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVB,	C_NSAUTO,C_NONE,	C_REG,	21, 4, REGSP },  // 
-	{ AMOVB,	C_ZOREG,C_NONE,	C_REG,		21, 4, 0 },  // 
-	{ AMOVB,	C_UOREG4K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVB,	C_NSOREG,C_NONE,	C_REG,	21, 4, REGSP },  // 
+	{ AMOVB,	C_SEXT1,	C_NONE,	C_REG,	C_NONE,		21, 4, REGSB },  // 
+	{ AMOVB,	C_UAUTO4K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVB,	C_NSAUTO,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
+	{ AMOVB,	C_ZOREG,C_NONE,	C_REG,	C_NONE,		21, 4, 0 },  // 
+	{ AMOVB,	C_UOREG4K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVB,	C_NSOREG,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
 
-	{ AMOVBU,	C_SEXT1,	C_NONE,	C_REG,		21, 4, REGSB },  // 
-	{ AMOVBU,	C_UAUTO4K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVBU,	C_NSAUTO,C_NONE,	C_REG,	21, 4, REGSP },  // 
-	{ AMOVBU,	C_ZOREG,C_NONE,	C_REG,		21, 4, 0 },  // 
-	{ AMOVBU,	C_UOREG4K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVBU,	C_NSOREG,C_NONE,	C_REG,	21, 4, REGSP },  // 
+	{ AMOVBU,	C_SEXT1,	C_NONE,	C_REG,	C_NONE,		21, 4, REGSB },  // 
+	{ AMOVBU,	C_UAUTO4K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVBU,	C_NSAUTO,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
+	{ AMOVBU,	C_ZOREG,C_NONE,	C_REG,	C_NONE,		21, 4, 0 },  // 
+	{ AMOVBU,	C_UOREG4K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVBU,	C_NSOREG,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
 
-	{ AMOVH,	C_SEXT2,	C_NONE,	C_REG,		21, 4, REGSB },  // 
-	{ AMOVH,	C_UAUTO8K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVH,	C_NSAUTO,C_NONE,	C_REG,	21, 4, REGSP },  // 
-	{ AMOVH,	C_ZOREG,C_NONE,	C_REG,		21, 4, 0 },  // 
-	{ AMOVH,	C_UOREG8K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVH,	C_NSOREG,C_NONE,	C_REG,	21, 4, REGSP },  // 
+	{ AMOVH,	C_SEXT2,	C_NONE,	C_REG,	C_NONE,		21, 4, REGSB },  // 
+	{ AMOVH,	C_UAUTO8K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVH,	C_NSAUTO,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
+	{ AMOVH,	C_ZOREG,C_NONE,	C_REG,	C_NONE,		21, 4, 0 },  // 
+	{ AMOVH,	C_UOREG8K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVH,	C_NSOREG,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
 
-	{ AMOVW,	C_SEXT4,	C_NONE,	C_REG,		21, 4, REGSB },  // 
-	{ AMOVW,	C_UAUTO16K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVW,	C_NSAUTO,C_NONE,	C_REG,	21, 4, REGSP },  // 
-	{ AMOVW,	C_ZOREG,C_NONE,	C_REG,		21, 4, 0 },  // 
-	{ AMOVW,	C_UOREG16K,C_NONE,	C_REG,		21, 4, REGSP },  // 
-	{ AMOVW,	C_NSOREG,C_NONE,	C_REG,	21, 4, REGSP },  // 
+	{ AMOVW,	C_SEXT4,	C_NONE,	C_REG,	C_NONE,		21, 4, REGSB },  // 
+	{ AMOVW,	C_UAUTO16K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVW,	C_NSAUTO,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
+	{ AMOVW,	C_ZOREG,C_NONE,	C_REG,	C_NONE,		21, 4, 0 },  // 
+	{ AMOVW,	C_UOREG16K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },  // 
+	{ AMOVW,	C_NSOREG,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },  // 
 
-	{ AMOV,	C_SEXT8,	C_NONE,	C_REG,		21, 4, REGSB },
-	{ AMOV,	C_UAUTO32K,C_NONE,	C_REG,		21, 4, REGSP },
-	{ AMOV,	C_NSAUTO,C_NONE,	C_REG,	21, 4, REGSP },
-	{ AMOV,	C_ZOREG,C_NONE,	C_REG,		21, 4, 0 },
-	{ AMOV,	C_UOREG32K,C_NONE,	C_REG,		21, 4, REGSP },
-	{ AMOV,	C_NSOREG,C_NONE,	C_REG,	21, 4, REGSP },
+	{ ALDPW,	C_SEXT4,	C_NONE,	C_REG,	C_REG,		49, 4, REGSB },  // 
+	{ ALDPW,	C_UAUTO16K,C_NONE,	C_REG,	C_REG,		49, 4, REGSP },  // 
+	{ ALDPW,	C_NSAUTO,C_NONE,	C_REG,	C_REG,	49, 4, REGSP },  // 
+	{ ALDPW,	C_ZOREG,C_NONE,	C_REG,	C_REG,		49, 4, 0 },  // 
+	{ ALDPW,	C_UOREG16K,C_NONE,	C_REG,	C_REG,		49, 4, REGSP },  // 
+	{ ALDPW,	C_NSOREG,C_NONE,	C_REG,	C_REG,	49, 4, REGSP },  // 
 
+	{ AMOV,	C_SEXT8,	C_NONE,	C_REG,	C_NONE,		21, 4, REGSB },
+	{ AMOV,	C_UAUTO32K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },
+	{ AMOV,	C_NSAUTO,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },
+	{ AMOV,	C_ZOREG,C_NONE,	C_REG,	C_NONE,		21, 4, 0 },
+	{ AMOV,	C_UOREG32K,C_NONE,	C_REG,	C_NONE,		21, 4, REGSP },
+	{ AMOV,	C_NSOREG,C_NONE,	C_REG,	C_NONE,	21, 4, REGSP },
+
+	{ ALDP,	C_SEXT8,	C_NONE,	C_REG,	C_REG,		21, 4, REGSB },
+	{ ALDP,	C_UAUTO32K,C_NONE,	C_REG,	C_REG,		21, 4, REGSP },
+	{ ALDP,	C_NSAUTO,C_NONE,	C_REG,	C_REG,	21, 4, REGSP },
+	{ ALDP,	C_ZOREG,C_NONE,	C_REG,	C_REG,		21, 4, 0 },
+	{ ALDP,	C_UOREG32K,C_NONE,	C_REG,	C_REG,		21, 4, REGSP },
+	{ ALDP,	C_NSOREG,C_NONE,	C_REG,	C_REG,	21, 4, REGSP },
+
 	/* large displacement store */
-	{ AMOVB,	C_REG,	C_NONE,	C_LEXT,		30, 8, REGSB,	LTO },
-	{ AMOVB,	C_REG,	C_NONE,	C_LAUTO,	30, 8, REGSP,	LTO },
-	{ AMOVB,	C_REG,	C_NONE,	C_LOREG,	30, 8, 0,	LTO },
-	{ AMOVBU,	C_REG,	C_NONE,	C_LEXT,		30, 8, REGSB,	LTO },
-	{ AMOVBU,	C_REG,	C_NONE,	C_LAUTO,	30, 8, REGSP,	LTO },
-	{ AMOVBU,	C_REG,	C_NONE,	C_LOREG,	30, 8, 0,	LTO },
+	{ AMOVB,	C_REG,	C_NONE,	C_LEXT,	C_NONE,		30, 8, REGSB,	LTO },
+	{ AMOVB,	C_REG,	C_NONE,	C_LAUTO,	C_NONE,	30, 8, REGSP,	LTO },
+	{ AMOVB,	C_REG,	C_NONE,	C_LOREG,	C_NONE,	30, 8, 0,	LTO },
+	{ AMOVBU,	C_REG,	C_NONE,	C_LEXT,	C_NONE,		30, 8, REGSB,	LTO },
+	{ AMOVBU,	C_REG,	C_NONE,	C_LAUTO,	C_NONE,	30, 8, REGSP,	LTO },
+	{ AMOVBU,	C_REG,	C_NONE,	C_LOREG,	C_NONE,	30, 8, 0,	LTO },
 
-	{ AMOVH,	C_REG,	C_NONE,	C_LEXT,		30, 8, REGSB,	LTO },
-	{ AMOVH,	C_REG,	C_NONE,	C_LAUTO,	30, 8, REGSP,	LTO },
-	{ AMOVH,	C_REG,	C_NONE,	C_LOREG,	30, 8, 0,	LTO },
+	{ AMOVH,	C_REG,	C_NONE,	C_LEXT,	C_NONE,		30, 8, REGSB,	LTO },
+	{ AMOVH,	C_REG,	C_NONE,	C_LAUTO,	C_NONE,	30, 8, REGSP,	LTO },
+	{ AMOVH,	C_REG,	C_NONE,	C_LOREG,	C_NONE,	30, 8, 0,	LTO },
 
-	{ AMOVW,	C_REG,	C_NONE,	C_LEXT,		30, 8, REGSB,	LTO },
-	{ AMOVW,	C_REG,	C_NONE,	C_LAUTO,	30, 8, REGSP,	LTO },
-	{ AMOVW,	C_REG,	C_NONE,	C_LOREG,	30, 8, 0,	LTO },
+	{ AMOVW,	C_REG,	C_NONE,	C_LEXT,	C_NONE,		30, 8, REGSB,	LTO },
+	{ AMOVW,	C_REG,	C_NONE,	C_LAUTO,	C_NONE,	30, 8, REGSP,	LTO },
+	{ AMOVW,	C_REG,	C_NONE,	C_LOREG,	C_NONE,	30, 8, 0,	LTO },
 
-	{ AMOV,		C_REG,	C_NONE,	C_LEXT,		30, 8, REGSB,	LTO },
-	{ AMOV,		C_REG,	C_NONE,	C_LAUTO,	30, 8, REGSP,	LTO },
-	{ AMOV,		C_REG,	C_NONE,	C_LOREG,	30, 8, 0,	LTO },
+	{ AMOV,		C_REG,	C_NONE,	C_LEXT,	C_NONE,		30, 8, REGSB,	LTO },
+	{ AMOV,		C_REG,	C_NONE,	C_LAUTO,	C_NONE,	30, 8, REGSP,	LTO },
+	{ AMOV,		C_REG,	C_NONE,	C_LOREG,	C_NONE,	30, 8, 0,	LTO },
 
 	/* large displacement load */
-	{ AMOVB,	C_LEXT,	C_NONE,	C_REG,		31, 8, REGSB,	LFROM  },
-	{ AMOVB,	C_LAUTO,C_NONE,	C_REG,		31, 8, REGSP,	LFROM  },
-	{ AMOVB,	C_LOREG,C_NONE,	C_REG,		31, 8, 0,	LFROM  },
-	{ AMOVBU,	C_LEXT,	C_NONE,	C_REG,		31, 8, REGSB,	LFROM  },
-	{ AMOVBU,	C_LAUTO,C_NONE,	C_REG,		31, 8, REGSP,	LFROM  },
-	{ AMOVBU,	C_LOREG,C_NONE,	C_REG,		31, 8, 0,	LFROM  },
+	{ AMOVB,	C_LEXT,	C_NONE,	C_REG,	C_NONE,		31, 8, REGSB,	LFROM  },
+	{ AMOVB,	C_LAUTO,C_NONE,	C_REG,	C_NONE,		31, 8, REGSP,	LFROM  },
+	{ AMOVB,	C_LOREG,C_NONE,	C_REG,	C_NONE,		31, 8, 0,	LFROM  },
+	{ AMOVBU,	C_LEXT,	C_NONE,	C_REG,	C_NONE,		31, 8, REGSB,	LFROM  },
+	{ AMOVBU,	C_LAUTO,C_NONE,	C_REG,	C_NONE,		31, 8, REGSP,	LFROM  },
+	{ AMOVBU,	C_LOREG,C_NONE,	C_REG,	C_NONE,		31, 8, 0,	LFROM  },
 
-	{ AMOVH,	C_LEXT,	C_NONE,	C_REG,		31, 8, REGSB,	LFROM  },
-	{ AMOVH,	C_LAUTO,C_NONE,	C_REG,		31, 8, REGSP,	LFROM  },
-	{ AMOVH,	C_LOREG,C_NONE,	C_REG,		31, 8, 0,	LFROM  },
+	{ AMOVH,	C_LEXT,	C_NONE,	C_REG,	C_NONE,		31, 8, REGSB,	LFROM  },
+	{ AMOVH,	C_LAUTO,C_NONE,	C_REG,	C_NONE,		31, 8, REGSP,	LFROM  },
+	{ AMOVH,	C_LOREG,C_NONE,	C_REG,	C_NONE,		31, 8, 0,	LFROM  },
 
-	{ AMOVW,	C_LEXT,	C_NONE,	C_REG,		31, 8, REGSB,	LFROM  },
-	{ AMOVW,	C_LAUTO,C_NONE,	C_REG,		31, 8, REGSP,	LFROM  },
-	{ AMOVW,	C_LOREG,C_NONE,	C_REG,		31, 8, 0,	LFROM  },
+	{ AMOVW,	C_LEXT,	C_NONE,	C_REG,	C_NONE,		31, 8, REGSB,	LFROM  },
+	{ AMOVW,	C_LAUTO,C_NONE,	C_REG,	C_NONE,		31, 8, REGSP,	LFROM  },
+	{ AMOVW,	C_LOREG,C_NONE,	C_REG,	C_NONE,		31, 8, 0,	LFROM  },
 
-	{ AMOV,		C_LEXT,	C_NONE,	C_REG,		31, 8, REGSB,	LFROM  },
-	{ AMOV,		C_LAUTO,C_NONE,	C_REG,		31, 8, REGSP,	LFROM  },
-	{ AMOV,		C_LOREG,C_NONE,	C_REG,		31, 8, 0,	LFROM  },
+	{ ALDPW,	C_LEXT,	C_NONE,	C_REG,	C_REG,		31, 8, REGSB,	LFROM  },
+	{ ALDPW,	C_LAUTO,C_NONE,	C_REG,	C_REG,		31, 8, REGSP,	LFROM  },
+	{ ALDPW,	C_LOREG,C_NONE,	C_REG,	C_REG,		31, 8, 0,	LFROM  },
 
+	{ AMOV,		C_LEXT,	C_NONE,	C_REG,	C_NONE,		31, 8, REGSB,	LFROM  },
+	{ AMOV,		C_LAUTO,C_NONE,	C_REG,	C_NONE,		31, 8, REGSP,	LFROM  },
+	{ AMOV,		C_LOREG,C_NONE,	C_REG,	C_NONE,		31, 8, 0,	LFROM  },
+
+	{ ALDP,		C_LEXT,	C_NONE,	C_REG,	C_NONE,		31, 8, REGSB,	LFROM  },
+	{ ALDP,		C_LAUTO,C_NONE,	C_REG,	C_NONE,		31, 8, REGSP,	LFROM  },
+	{ ALDP,		C_LOREG,C_NONE,	C_REG,	C_NONE,		31, 8, 0,	LFROM  },
+
 	/* load large effective stack address (load large offset and add) */
-	{ AMOV,		C_LACON,C_NONE,	C_REG,		34, 8, REGSP,	LFROM },
+	{ AMOV,		C_LACON,C_NONE,	C_REG,	C_NONE,		34, 8, REGSP,	LFROM },
 
 	/* pre/post-indexed load (unscaled, signed 9-bit offset) */
-	{ AMOV,		C_XPOST,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVW, 	C_XPOST,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVH,	C_XPOST,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVB, 	C_XPOST,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVBU, 	C_XPOST,	C_NONE, C_REG,		22, 4, 0 },
-	{ AFMOVS, 	C_XPOST,	C_NONE,	C_FREG,	22, 4, 0 },
-	{ AFMOVD, 	C_XPOST,	C_NONE,	C_FREG,	22, 4, 0 },
+	{ AMOV,		C_XPOST,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVW, 	C_XPOST,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVH,	C_XPOST,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVB, 	C_XPOST,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVBU, 	C_XPOST,	C_NONE, C_REG,	C_NONE,		22, 4, 0 },
+	{ AFMOVS, 	C_XPOST,	C_NONE,	C_FREG,	C_NONE,	22, 4, 0 },
+	{ AFMOVD, 	C_XPOST,	C_NONE,	C_FREG,	C_NONE,	22, 4, 0 },
 
-	{ AMOV,		C_XPRE,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVW, 	C_XPRE,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVH,	C_XPRE,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVB, 	C_XPRE,	C_NONE,	C_REG,		22, 4, 0 },
-	{ AMOVBU, 	C_XPRE,	C_NONE, C_REG,		22, 4, 0 },
-	{ AFMOVS, 	C_XPRE,	C_NONE,	C_FREG,	22, 4, 0 },
-	{ AFMOVD, 	C_XPRE,	C_NONE,	C_FREG,	22, 4, 0 },
+	{ AMOV,		C_XPRE,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVW, 	C_XPRE,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVH,	C_XPRE,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVB, 	C_XPRE,	C_NONE,	C_REG,	C_NONE,		22, 4, 0 },
+	{ AMOVBU, 	C_XPRE,	C_NONE, C_REG,	C_NONE,		22, 4, 0 },
+	{ AFMOVS, 	C_XPRE,	C_NONE,	C_FREG,	C_NONE,	22, 4, 0 },
+	{ AFMOVD, 	C_XPRE,	C_NONE,	C_FREG,	C_NONE,	22, 4, 0 },
 
 	/* pre/post-indexed store (unscaled, signed 9-bit offset) */
-	{ AMOV,		C_REG,	C_NONE,	C_XPOST,		23, 4, 0 },
-	{ AMOVW,		C_REG,	C_NONE,	C_XPOST,		23, 4, 0 },
-	{ AMOVH,		C_REG,	C_NONE,	C_XPOST,		23, 4, 0 },
-	{ AMOVB,		C_REG,	C_NONE, C_XPOST,		23, 4, 0 },
-	{ AMOVBU, 	C_REG,	C_NONE, C_XPOST,		23, 4, 0 },
-	{ AFMOVS, 	C_FREG,	C_NONE,	C_XPOST,		23, 4, 0 },
-	{ AFMOVD, 	C_FREG,	C_NONE,	C_XPOST,		23, 4, 0 },
+	{ AMOV,		C_REG,	C_NONE,	C_XPOST,	C_NONE,		23, 4, 0 },
+	{ AMOVW,		C_REG,	C_NONE,	C_XPOST,	C_NONE,		23, 4, 0 },
+	{ AMOVH,		C_REG,	C_NONE,	C_XPOST,	C_NONE,		23, 4, 0 },
+	{ AMOVB,		C_REG,	C_NONE, C_XPOST,	C_NONE,		23, 4, 0 },
+	{ AMOVBU, 	C_REG,	C_NONE, C_XPOST,	C_NONE,		23, 4, 0 },
+	{ AFMOVS, 	C_FREG,	C_NONE,	C_XPOST,	C_NONE,		23, 4, 0 },
+	{ AFMOVD, 	C_FREG,	C_NONE,	C_XPOST,	C_NONE,		23, 4, 0 },
 
-	{ AMOV,		C_REG,	C_NONE,	C_XPRE,		23, 4, 0 },
-	{ AMOVW,		C_REG,	C_NONE,	C_XPRE,		23, 4, 0 },
-	{ AMOVH,		C_REG,	C_NONE,	C_XPRE,		23, 4, 0 },
-	{ AMOVB,		C_REG,	C_NONE, C_XPRE,		23, 4, 0 },
-	{ AMOVBU, 	C_REG,	C_NONE, C_XPRE,		23, 4, 0 },
-	{ AFMOVS, 	C_FREG,	C_NONE,	C_XPRE,		23, 4, 0 },
-	{ AFMOVD, 	C_FREG,	C_NONE,	C_XPRE,		23, 4, 0 },
+	{ AMOV,		C_REG,	C_NONE,	C_XPRE,	C_NONE,		23, 4, 0 },
+	{ AMOVW,		C_REG,	C_NONE,	C_XPRE,	C_NONE,		23, 4, 0 },
+	{ AMOVH,		C_REG,	C_NONE,	C_XPRE,	C_NONE,		23, 4, 0 },
+	{ AMOVB,		C_REG,	C_NONE, C_XPRE,	C_NONE,		23, 4, 0 },
+	{ AMOVBU, 	C_REG,	C_NONE, C_XPRE,	C_NONE,		23, 4, 0 },
+	{ AFMOVS, 	C_FREG,	C_NONE,	C_XPRE,	C_NONE,		23, 4, 0 },
+	{ AFMOVD, 	C_FREG,	C_NONE,	C_XPRE,	C_NONE,		23, 4, 0 },
 
-	{ AMOVP, 	C_PPAUTO,	C_REG,	C_REG,		66, 4, 0 },
-	{ AMOVP, 	C_PPOREG,	C_REG,	C_REG,		66, 4, 0 },
-	{ AMOVP, 	C_NPAUTO,	C_REG,	C_REG,		66, 4, 0 },
-	{ AMOVP, 	C_NPOREG,	C_REG,	C_REG,		66, 4, 0 },
-	{ AMOVP, 	C_XPOST,	C_REG,	C_REG,		66, 4, 0 },
-	{ AMOVP, 	C_XPRE,		C_REG,	C_REG,		66, 4, 0 },
+	{ AMOVP, 	C_PPAUTO,	C_REG,	C_REG,	C_NONE,		66, 4, 0 },
+	{ AMOVP, 	C_PPOREG,	C_REG,	C_REG,	C_NONE,		66, 4, 0 },
+	{ AMOVP, 	C_NPAUTO,	C_REG,	C_REG,	C_NONE,		66, 4, 0 },
+	{ AMOVP, 	C_NPOREG,	C_REG,	C_REG,	C_NONE,		66, 4, 0 },
+	{ AMOVP, 	C_XPOST,	C_REG,	C_REG,	C_NONE,		66, 4, 0 },
+	{ AMOVP, 	C_XPRE,		C_REG,	C_REG,	C_NONE,		66, 4, 0 },
 
-	{ AMOVP, 	C_REG,		C_REG, C_PPAUTO,	67, 4, 0 },
-	{ AMOVP, 	C_REG,		C_REG, C_PPOREG,	67, 4, 0 },
-	{ AMOVP, 	C_REG,		C_REG, C_NPAUTO,	67, 4, 0 },
-	{ AMOVP, 	C_REG,		C_REG, C_NPOREG,	67, 4, 0 },
-	{ AMOVP, 	C_REG,		C_REG, C_XPOST,		67, 4, 0 },
-	{ AMOVP, 	C_REG,		C_REG, C_XPRE,		67, 4, 0 },
+	{ AMOVP, 	C_REG,		C_REG, C_PPAUTO,	C_NONE,	67, 4, 0 },
+	{ AMOVP, 	C_REG,		C_REG, C_PPOREG,	C_NONE,	67, 4, 0 },
+	{ AMOVP, 	C_REG,		C_REG, C_NPAUTO,	C_NONE,	67, 4, 0 },
+	{ AMOVP, 	C_REG,		C_REG, C_NPOREG,	C_NONE,	67, 4, 0 },
+	{ AMOVP, 	C_REG,		C_REG, C_XPOST,	C_NONE,		67, 4, 0 },
+	{ AMOVP, 	C_REG,		C_REG, C_XPRE,	C_NONE,		67, 4, 0 },
 
 	/* special */
-	{ AMOV,		C_SPR,	C_NONE,	C_REG,		35, 4, 0 },
-	{ AMRS,		C_SPR,	C_NONE,	C_REG,		35, 4, 0 },
+	{ AMOV,		C_SPR,	C_NONE,	C_REG,	C_NONE,		35, 4, 0 },
+	{ AMRS,		C_SPR,	C_NONE,	C_REG,	C_NONE,		35, 4, 0 },
 
-	{ AMOV,		C_REG,	C_NONE,	C_SPR,		36, 4, 0 },
-	{ AMSR,		C_REG,	C_NONE,	C_SPR,		36, 4, 0 },
+	{ AMOV,		C_REG,	C_NONE,	C_SPR,	C_NONE,		36, 4, 0 },
+	{ AMSR,		C_REG,	C_NONE,	C_SPR,	C_NONE,		36, 4, 0 },
 
-	{ AMOV,		C_LCON,	C_NONE,	C_SPR,		37, 4, 0 },
-	{ AMSR,		C_LCON,	C_NONE,	C_SPR,		37, 4, 0 },
+	{ AMOV,		C_LCON,	C_NONE,	C_SPR,	C_NONE,		37, 4, 0 },
+	{ AMSR,		C_LCON,	C_NONE,	C_SPR,	C_NONE,		37, 4, 0 },
 
-	{ AERET,		C_NONE,	C_NONE,	C_NONE,		41, 4, 0 },
+	{ AERET,		C_NONE,	C_NONE,	C_NONE,	C_NONE,		41, 4, 0 },
 
-	{ AFMOVS,	C_FREG,	C_NONE,	C_SEXT4,		20, 4, REGSB },
-	{ AFMOVS,	C_FREG,	C_NONE,	C_UAUTO16K,	20, 4, REGSP },
-	{ AFMOVS,	C_FREG,	C_NONE,	C_NSAUTO,	20, 4, REGSP },
-	{ AFMOVS,	C_FREG,	C_NONE,	C_ZOREG,		20, 4, 0 },
-	{ AFMOVS,	C_FREG,	C_NONE,	C_UOREG16K,	20, 4, 0 },
-	{ AFMOVS,	C_FREG,	C_NONE,	C_NSOREG,	20, 4, 0 },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_SEXT4,	C_NONE,		20, 4, REGSB },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_UAUTO16K,	C_NONE,	20, 4, REGSP },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_NSAUTO,	C_NONE,	20, 4, REGSP },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_ZOREG,	C_NONE,		20, 4, 0 },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_UOREG16K,	C_NONE,	20, 4, 0 },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_NSOREG,	C_NONE,	20, 4, 0 },
 
-	{ AFMOVD,	C_FREG,	C_NONE,	C_SEXT8,		20, 4, REGSB },
-	{ AFMOVD,	C_FREG,	C_NONE,	C_UAUTO32K,	20, 4, REGSP },
-	{ AFMOVD,	C_FREG,	C_NONE,	C_NSAUTO,	20, 4, REGSP },
-	{ AFMOVD,	C_FREG,	C_NONE,	C_ZOREG,		20, 4, 0 },
-	{ AFMOVD,	C_FREG,	C_NONE,	C_UOREG32K,	20, 4, 0 }, 
-	{ AFMOVD,	C_FREG,	C_NONE,	C_NSOREG,	20, 4, 0 },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_SEXT8,	C_NONE,		20, 4, REGSB },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_UAUTO32K,	C_NONE,	20, 4, REGSP },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_NSAUTO,	C_NONE,	20, 4, REGSP },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_ZOREG,	C_NONE,		20, 4, 0 },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_UOREG32K,	C_NONE,	20, 4, 0 }, 
+	{ AFMOVD,	C_FREG,	C_NONE,	C_NSOREG,	C_NONE,	20, 4, 0 },
 
-	{ AFMOVS,	C_SEXT4,	C_NONE,	C_FREG,		21, 4, REGSB },
-	{ AFMOVS,	C_UAUTO16K,C_NONE,	C_FREG,		21, 4, REGSP },
-	{ AFMOVS,	C_NSAUTO,C_NONE,	C_FREG,		21, 4, REGSP },
-	{ AFMOVS,	C_ZOREG,C_NONE,	C_FREG,		21, 4, 0 },
-	{ AFMOVS,	C_UOREG16K,C_NONE,	C_FREG,		21, 4, 0 },
-	{ AFMOVS,	C_NSOREG,C_NONE,	C_FREG,		21, 4, 0 },
+	{ AFMOVS,	C_SEXT4,	C_NONE,	C_FREG,	C_NONE,		21, 4, REGSB },
+	{ AFMOVS,	C_UAUTO16K,C_NONE,	C_FREG,	C_NONE,		21, 4, REGSP },
+	{ AFMOVS,	C_NSAUTO,C_NONE,	C_FREG,	C_NONE,		21, 4, REGSP },
+	{ AFMOVS,	C_ZOREG,C_NONE,	C_FREG,	C_NONE,		21, 4, 0 },
+	{ AFMOVS,	C_UOREG16K,C_NONE,	C_FREG,	C_NONE,		21, 4, 0 },
+	{ AFMOVS,	C_NSOREG,C_NONE,	C_FREG,	C_NONE,		21, 4, 0 },
 
-	{ AFMOVD,	C_SEXT8,	C_NONE,	C_FREG,		21, 4, REGSB },
-	{ AFMOVD,	C_UAUTO32K,C_NONE,	C_FREG,		21, 4, REGSP },
-	{ AFMOVD,	C_NSAUTO,C_NONE,	C_FREG,		21, 4, REGSP },
-	{ AFMOVD,	C_ZOREG,C_NONE,	C_FREG,		21, 4, 0 },
-	{ AFMOVD,	C_UOREG32K,C_NONE,	C_FREG,		21, 4, 0 },
-	{ AFMOVD,	C_NSOREG,C_NONE,	C_FREG,		21, 4, 0 },
+	{ AFLDPS,	C_SEXT4,	C_NONE,	C_FREG,	C_FREG,		21, 4, REGSB },
+	{ AFLDPS,	C_UAUTO16K,C_NONE,	C_FREG,	C_FREG,		21, 4, REGSP },
+	{ AFLDPS,	C_NSAUTO,C_NONE,	C_FREG,	C_FREG,		21, 4, REGSP },
+	{ AFLDPS,	C_ZOREG,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
+	{ AFLDPS,	C_UOREG16K,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
+	{ AFLDPS,	C_NSOREG,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
 
-	{ AFMOVS,	C_FREG,	C_NONE,	C_LEXT,		30, 8, REGSB,	LTO },
-	{ AFMOVS,	C_FREG,	C_NONE,	C_LAUTO,	30, 8, REGSP,	LTO },
-	{ AFMOVS,	C_FREG,	C_NONE,	C_LOREG,	30, 8, 0,	LTO },
+	{ AFMOVD,	C_SEXT8,	C_NONE,	C_FREG,	C_FREG,		21, 4, REGSB },
+	{ AFMOVD,	C_UAUTO32K,C_NONE,	C_FREG,	C_FREG,		21, 4, REGSP },
+	{ AFMOVD,	C_NSAUTO,C_NONE,	C_FREG,	C_FREG,		21, 4, REGSP },
+	{ AFMOVD,	C_ZOREG,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
+	{ AFMOVD,	C_UOREG32K,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
+	{ AFMOVD,	C_NSOREG,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
 
-	{ AFMOVD,	C_FREG,	C_NONE,	C_LEXT,		30, 8, REGSB,	LTO },
-	{ AFMOVD,	C_FREG,	C_NONE,	C_LAUTO,	30, 8, REGSP,	LTO },
-	{ AFMOVD,	C_FREG,	C_NONE,	C_LOREG,	30, 8, 0,	LTO },
+	{ AFLDPD,	C_SEXT8,	C_NONE,	C_FREG,	C_FREG,		21, 4, REGSB },
+	{ AFLDPD,	C_UAUTO32K,C_NONE,	C_FREG,	C_FREG,		21, 4, REGSP },
+	{ AFLDPD,	C_NSAUTO,C_NONE,	C_FREG,	C_FREG,		21, 4, REGSP },
+	{ AFLDPD,	C_ZOREG,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
+	{ AFLDPD,	C_UOREG32K,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
+	{ AFLDPD,	C_NSOREG,C_NONE,	C_FREG,	C_FREG,		21, 4, 0 },
 
-	{ AFMOVS,	C_LEXT,	C_NONE,	C_FREG,		31, 8, REGSB,	LFROM },
-	{ AFMOVS,	C_LAUTO,C_NONE,	C_FREG,		31, 8, REGSP,	LFROM },
-	{ AFMOVS,	C_LOREG,C_NONE,	C_FREG,		31, 8, 0,	LFROM },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_LEXT,	C_NONE,		30, 8, REGSB,	LTO },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_LAUTO,	C_NONE,	30, 8, REGSP,	LTO },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_LOREG,	C_NONE,	30, 8, 0,	LTO },
 
-	{ AFMOVD,	C_LEXT,	C_NONE,	C_FREG,		31, 8, REGSB,	LFROM },
-	{ AFMOVD,	C_LAUTO,C_NONE,	C_FREG,		31, 8, REGSP,	LFROM },
-	{ AFMOVD,	C_LOREG,C_NONE,	C_FREG,		31, 8, 0,	LFROM },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_LEXT,	C_NONE,		30, 8, REGSB,	LTO },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_LAUTO,	C_NONE,	30, 8, REGSP,	LTO },
+	{ AFMOVD,	C_FREG,	C_NONE,	C_LOREG,	C_NONE,	30, 8, 0,	LTO },
 
-	{ AFMOVS,	C_FREG,	C_NONE,	C_ADDR,		64, 8, 0,	LTO },
-	{ AFMOVS,	C_ADDR,	C_NONE,	C_FREG,		65, 8, 0,	LFROM },
+	{ AFMOVS,	C_LEXT,	C_NONE,	C_FREG,	C_NONE,		31, 8, REGSB,	LFROM },
+	{ AFMOVS,	C_LAUTO,C_NONE,	C_FREG,	C_NONE,		31, 8, REGSP,	LFROM },
+	{ AFMOVS,	C_LOREG,C_NONE,	C_FREG,	C_NONE,		31, 8, 0,	LFROM },
 
-	{ AFADDS,	C_FREG,	C_NONE,	C_FREG,		54, 4, 0 },
-	{ AFADDS,	C_FREG,	C_REG,	C_FREG,		54, 4, 0 },
-	{ AFADDS,	C_FCON,	C_NONE,	C_FREG,		54, 4, 0 },
-	{ AFADDS,	C_FCON,	C_REG,	C_FREG,		54, 4, 0 },
+	{ AFLDPS,	C_LEXT,	C_NONE,	C_FREG,	C_FREG,		31, 8, REGSB,	LFROM },
+	{ AFLDPS,	C_LAUTO,C_NONE,	C_FREG,	C_FREG,		31, 8, REGSP,	LFROM },
+	{ AFLDPS,	C_LOREG,C_NONE,	C_FREG,	C_FREG,		31, 8, 0,	LFROM },
 
-	{ AFMOVS,	C_FCON,	C_NONE,	C_FREG,		54, 4, 0 },
-	{ AFMOVS,	C_FREG, C_NONE, C_FREG,		54, 4, 0 },
-	{ AFMOVD,	C_FCON,	C_NONE,	C_FREG,		54, 4, 0 },
-	{ AFMOVD,	C_FREG, C_NONE, C_FREG,		54, 4, 0 },
+	{ AFMOVD,	C_LEXT,	C_NONE,	C_FREG,	C_NONE,		31, 8, REGSB,	LFROM },
+	{ AFMOVD,	C_LAUTO,C_NONE,	C_FREG,	C_NONE,		31, 8, REGSP,	LFROM },
+	{ AFMOVD,	C_LOREG,C_NONE,	C_FREG,	C_NONE,		31, 8, 0,	LFROM },
 
-	{ AFCVTZSD,	C_FREG,	C_NONE,	C_REG,		29, 4, 0 },
-	{ ASCVTFD,	C_REG,	C_NONE,	C_FREG,		29, 4, 0 },
+	{ AFLDPD,	C_LEXT,	C_NONE,	C_FREG,	C_FREG,		31, 8, REGSB,	LFROM },
+	{ AFLDPD,	C_LAUTO,C_NONE,	C_FREG,	C_FREG,		31, 8, REGSP,	LFROM },
+	{ AFLDPD,	C_LOREG,C_NONE,	C_FREG,	C_FREG,		31, 8, 0,	LFROM },
 
-	{ AFCMPS,		C_FREG,	C_REG,	C_NONE,		56, 4, 0 },
-	{ AFCMPS,		C_FCON,	C_REG,	C_NONE,		56, 4, 0 },
+	{ AFMOVS,	C_FREG,	C_NONE,	C_ADDR,	C_NONE,		64, 8, 0,	LTO },
+	{ AFMOVS,	C_ADDR,	C_NONE,	C_FREG,	C_NONE,		65, 8, 0,	LFROM },
 
-	{ AFCCMPS,	C_COND,	C_REG,	C_LCON,		57, 4, 0 },
+	{ AFADDS,	C_FREG,	C_NONE,	C_FREG,	C_NONE,		54, 4, 0 },
+	{ AFADDS,	C_FREG,	C_REG,	C_FREG,	C_NONE,		54, 4, 0 },
+	{ AFADDS,	C_FCON,	C_NONE,	C_FREG,	C_NONE,		54, 4, 0 },
+	{ AFADDS,	C_FCON,	C_REG,	C_FREG,	C_NONE,		54, 4, 0 },
 
-	{ AFCSELD,	C_COND,	C_REG,	C_FREG,		18, 4, 0 },
+	{ AFMOVS,	C_FCON,	C_NONE,	C_FREG,	C_NONE,		54, 4, 0 },
+	{ AFMOVS,	C_FREG, C_NONE, C_FREG,	C_NONE,		54, 4, 0 },
+	{ AFMOVD,	C_FCON,	C_NONE,	C_FREG,	C_NONE,		54, 4, 0 },
+	{ AFMOVD,	C_FREG, C_NONE, C_FREG,	C_NONE,		54, 4, 0 },
 
-	{ AFCVTSD,	C_FREG,	C_NONE,	C_FREG,		29, 4, 0 },
+	{ AFCVTZSD,	C_FREG,	C_NONE,	C_REG,	C_NONE,		29, 4, 0 },
+	{ ASCVTFD,	C_REG,	C_NONE,	C_FREG,	C_NONE,		29, 4, 0 },
 
-	{ ACASE,	C_REG,	C_NONE,	C_REG,		62, 4*4, 0 },
-	{ ABCASE,	C_NONE, C_NONE, C_SBRA,		63, 4, 0 },
+	{ AFCMPS,		C_FREG,	C_REG,	C_NONE,	C_NONE,		56, 4, 0 },
+	{ AFCMPS,		C_FCON,	C_REG,	C_NONE,	C_NONE,		56, 4, 0 },
 
-	{ ACLREX,		C_NONE,	C_NONE,	C_LCON,		38, 4, 0 },
-	{ ACLREX,		C_NONE,	C_NONE,	C_NONE,		38, 4, 0 },
+	{ AFCCMPS,	C_COND,	C_REG,	C_LCON,	C_NONE,		57, 4, 0 },
 
-	{ ACBZ,		C_REG,	C_NONE,	C_SBRA,		39, 4, 0 },
-	{ ATBZ,		C_LCON,	C_REG,	C_SBRA,		40, 4, 0 },
+	{ AFCSELD,	C_COND,	C_REG,	C_FREG,	C_NONE,		18, 4, 0 },
 
-	{ ASYS,		C_LCON,	C_NONE,	C_NONE,		50, 4, 0 },
-	{ ASYS,		C_LCON,	C_REG,	C_NONE,		50, 4, 0 },
-	{ ASYSL,		C_LCON,	C_NONE,	C_REG,		50, 4, 0 },
+	{ AFCVTSD,	C_FREG,	C_NONE,	C_FREG,	C_NONE,		29, 4, 0 },
 
-	{ ADMB,		C_LCON,	C_NONE, 	C_NONE,		51, 4, 0 },
-	{ AHINT,		C_LCON,	C_NONE,	C_NONE,		52, 4, 0 },
+	{ ACASE,	C_REG,	C_NONE,	C_REG,	C_NONE,		62, 4*4, 0 },
+	{ ABCASE,	C_NONE, C_NONE, C_SBRA,	C_NONE,		63, 4, 0 },
 
-	{ ALDXR,		C_ZOREG,	C_NONE,	C_REG,		58, 4, 0 },
-	{ ALDXP,		C_ZOREG,	C_REG,	C_REG,		58, 4, 0 },
-	{ ASTXR,		C_REG,	C_REG,	C_ZOREG,		59, 4, 0 },
-	{ ASTXP,		C_REG, C_REG,	C_ZOREG,		59, 4, 0 },
+	{ ACLREX,		C_NONE,	C_NONE,	C_LCON,	C_NONE,		38, 4, 0 },
+	{ ACLREX,		C_NONE,	C_NONE,	C_NONE,	C_NONE,		38, 4, 0 },
 
-	{ AAESD,	C_VREG,	C_NONE,	C_VREG,	29, 4, 0 },
-	{ ASHA1C,	C_VREG,	C_REG,	C_VREG,	1, 4, 0 },
+	{ ACBZ,		C_REG,	C_NONE,	C_SBRA,	C_NONE,		39, 4, 0 },
+	{ ATBZ,		C_LCON,	C_REG,	C_SBRA,	C_NONE,		40, 4, 0 },
 
-	{ AXXX,		C_NONE,	C_NONE,	C_NONE,		 0, 4, 0 },
+	{ ASYS,		C_LCON,	C_NONE,	C_NONE,	C_NONE,		50, 4, 0 },
+	{ ASYS,		C_LCON,	C_REG,	C_NONE,	C_NONE,		50, 4, 0 },
+	{ ASYSL,		C_LCON,	C_NONE,	C_REG,	C_NONE,		50, 4, 0 },
+
+	{ ADMB,		C_LCON,	C_NONE, 	C_NONE,	C_NONE,		51, 4, 0 },
+	{ AHINT,		C_LCON,	C_NONE,	C_NONE,	C_NONE,		52, 4, 0 },
+
+	{ ALDXR,		C_ZOREG,	C_NONE,	C_REG,	C_NONE,		58, 4, 0 },
+	{ ALDXP,		C_ZOREG,	C_REG,	C_REG,	C_NONE,		58, 4, 0 },
+	{ ASTXR,		C_REG,	C_REG,	C_ZOREG,	C_NONE,		59, 4, 0 },
+	{ ASTXP,		C_REG, C_REG,	C_ZOREG,	C_NONE,		59, 4, 0 },
+
+	{ AAESD,	C_VREG,	C_NONE,	C_VREG,	C_NONE,	29, 4, 0 },
+	{ ASHA1C,	C_VREG,	C_REG,	C_VREG,	C_NONE,	1, 4, 0 },
+
+	{ AXXX,		C_NONE,	C_NONE,	C_NONE,	C_NONE,		 0, 4, 0 },
 };
--- a/sys/src/cmd/7l/span.c
+++ b/sys/src/cmd/7l/span.c
@@ -206,9 +206,9 @@
 	t = zprg;
 	t.as = AWORD;
 	sz = 4;
-	switch(aclass(a)) {
+	switch(aclass(a)){
 	default:
-		if(p->as == AMOV && (a->name == D_EXTERN || a->name == D_STATIC)
+		if((p->as == AMOV || p->as == ALDP) && (a->name == D_EXTERN || a->name == D_STATIC)
 		|| (a->offset >> 32) != 0 && (a->offset >> 31) != -1){
 			t.as = ADWORD;
 			sz = 8;
@@ -695,8 +695,8 @@
 Optab*
 oplook(Prog *p)
 {
-	int a1, a2, a3, r;
-	char *c1, *c2, *c3;
+	int a1, a2, a3, a4, r;
+	char *c1, *c2, *c3, *c4;
 	Optab *o, *e;
 
 	a1 = p->optab;
@@ -714,6 +714,12 @@
 		p->to.class = a3;
 	}
 	a3--;
+	a4 = p->from3.class;
+	if(a4 == 0) {
+		a4 = aclass(&p->from3) + 1;
+		p->from3.class = a4;
+	}
+	a4--;
 	a2 = C_NONE;
 	if(p->reg != NREG)
 		a2 = C_REG;
@@ -736,18 +742,19 @@
 	c1 = xcmp[a1];
 	c2 = xcmp[a2];
 	c3 = xcmp[a3];
+	c4 = xcmp[a4];
 	for(; o<e; o++)
 		if(o->a2 == a2 || c2[o->a2])
 		if(c1[o->a1])
 		if(c3[o->a3]) {
 			if(0)
-				print("%P\t-> %d (%d %d %d)\n", p, o->type,
-					o->a1, o->a2, o->a3);
+				print("%P\t-> %d (%d %d %d %d)\n", p, o->type,
+					o->a1, o->a2, o->a3, o->a4);
 			p->optab = (o-optab)+1;
 			return o;
 		}
-	diag("illegal combination %A %R %R %R",
-		p->as, a1, a2, a3);
+	diag("illegal combination %A %R %R %R %R",
+		p->as, a1, a2, a3, a4);
 	prasm(p);
 	o = badop;
 	if(o == 0)
@@ -1106,6 +1113,9 @@
 		case AMOVW:
 			oprange[AMOVWU] = t;
 			break;
+		case ALDPW:
+			oprange[ALDPWU] = t;
+			break;
 		case ABFM:
 			oprange[ABFMW] = t;
 			oprange[ASBFM] = t;
@@ -1167,6 +1177,7 @@
 			oprange[ACSETM] = t;
 			oprange[ACSETMW] = t;
 			break;
+		case ALDP:
 		case AMOV:
 		case AMOVB:
 		case AMOVBU:
@@ -1272,6 +1283,8 @@
 
 		case AFMOVS:
 		case AFMOVD:
+		case AFLDPS:
+		case AFLDPD:
 			break;
 
 		case AFCVTZSD: