OK, turing.

<- leave blank

Sun Feb 28 12:11:13 EST 2021

diff -r 4bafb394707a sys/src/9/pc/devpccard.c
--- a/sys/src/9/pc/devpccard.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/pc/devpccard.c Sun Feb 28 18:11:13 2021 +0100
@@ -520,7 +520,6 @@
	static int initialized;
	Pcidev *pci;
	int i;
- uchar intl;
	char *p;

	if (initialized)
@@ -539,9 +538,9 @@

	/* Find all CardBus controllers */
	pci = nil;
- intl = 0xff;
	while ((pci = pcimatch(pci, 0, 0)) != nil) {
		uvlong baddr;
+ int size;
		Cardbus *cb;
		uchar pin;

@@ -633,23 +632,20 @@
			pcicfgw8(cb->pci, 0xD4, 0xCA);
		}

- baddr = pcicfgr32(cb->pci, PciBAR0);
- if (baddr == 0) {
- int size = (pci->did == Ricoh_478_did)?  0x10000: 0x1000;
+ size = (pci->did == Ricoh_478_did)?  0x10000: 0x1000;
+ baddr = (ulong)pcicfgr32(cb->pci, PciBAR0);
+ if (baddr == 0 || upaalloc(baddr, size, 0) == -1) {
			baddr = upaalloc(-1ULL, size, size);
			if(baddr == -1)
				continue;
			pcicfgw32(cb->pci, PciBAR0, (ulong)baddr);
- cb->regs = (ulong *)vmap(baddr, size);
		}
- else
- cb->regs = (ulong *)vmap(baddr, 4096);
+ cb->regs = (ulong *)vmap(baddr, size);
		if(cb->regs == nil)
			continue;
		cb->state = SlotEmpty;

- if (intl != 0xff && intl != pci->intl)
- intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");
+ intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");

		/* Don't really know what to do with this...  */
		i82365probe(cb, LegacyAddr, LegacyAddr + 1);
@@ -777,10 +773,8 @@
 static void
 configure(Cardbus *cb)
 {
- int i, r;
- Pcidev *pci;
- uvlong romlen, memlen, membase, rombase, bar;
- ulong iobase, iolen, size;
+ ulong iobase, iolen;
+ uvlong membase, memlen;

	if(DEBUG)
		print("configuring slot %ld (%s)\n", cb - cbslots,
		states[cb->state]);
@@ -796,104 +790,55 @@
	}

	/* Scan the CardBus for new PCI devices */
- pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge);
+ pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge, cb->pci);

- /*
- * size the devices on the bus, reserve a minimum for devices arriving later,
- * allow for ROM space, allocate space, and set the cardbus mapping registers
- */
- pcibussize(cb->pci->bridge, &memlen, &iolen); /* TO DO: need initial
alignments */
-
- romlen = 0;
- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- size = pcibarsize(pci, PciEBAR0);
- if(size > 0){
- pci->rom.bar = -1;
- pci->rom.size = size;
- romlen += size;
- }
- }
+ /* size the devices on the bus, reserve a minimum for devices arriving later */
+ pcibussize(cb->pci->bridge, &memlen, &iolen);

	if(iolen < 512)
		iolen = 512;
- iobase = ioreserve(-1, iolen, 0, "cardbus");
- if(iobase == -1)
- return;
-
- rombase = memlen;
- memlen += romlen;
	if(memlen < 1*1024*1024)
		memlen = 1*1024*1024;
- membase = upaalloc(-1ULL, memlen, 4*1024*1024); /* TO DO: better alignment */
- if(membase == -1)
+
+ print("#Y: slot %d, iolen=%lud, memlen=%llud\n", (int)(cb - cbslots), iolen,
memlen);
+ if(cb->pci->parent == nil){
+ iobase = ioreserve(-1, iolen, 0, "cardbus");
+ if(iobase == -1){
+NoIO:
+ print("#Y: slot %d, can't allocate io space\n", (int)(cb - cbslots));
+ return;
+ }
+ membase = upaalloc(-1ULL, memlen, 4*1024*1024);
+ } else {
+ iobase = ioreservewin(cb->pci->parent->ioa.bar,
cb->pci->parent->ioa.size, iolen, "cardbus");
+ if(iobase == -1)
+ goto NoIO;
+ membase = upaallocwin(cb->pci->parent->mema.bar,
cb->pci->parent->mema.size, memlen, 4*1024*1024);
+ }
+ if(membase == -1){
+ print("#Y: slot %d, can't allocate memory space\n", (int)(cb - cbslots));
		return;
+ }
+ print("#Y: slot %d, iobase=%lux, membase=%llux\n", (int)(cb - cbslots), iobase,
membase);

	pcicfgw32(cb->pci, PciCBIBR0, iobase);
	pcicfgw32(cb->pci, PciCBILR0, iobase + iolen-1);
	pcicfgw32(cb->pci, PciCBIBR1, 0);
	pcicfgw32(cb->pci, PciCBILR1, 0);
+ cb->pci->ioa.bar = iobase;
+ cb->pci->ioa.size = iolen;

	pcicfgw32(cb->pci, PciCBMBR0, (ulong)membase);
	pcicfgw32(cb->pci, PciCBMLR0, (ulong)membase + memlen-1);
	pcicfgw32(cb->pci, PciCBMBR1, 0);
	pcicfgw32(cb->pci, PciCBMLR1, 0);
+ cb->pci->mema.bar = membase;
+ cb->pci->mema.size = memlen;

-// pcibussize(cb->pci->bridge, &membase, &iobase); /* now assign them */
- rombase += membase;
+ /* Route interrupts to INTA#/B# */
+ pcicfgw16(cb->pci, PciBCR, pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));

- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- r = pcicfgr16(pci, PciPCR);
- r &= ~(PciPCR_IO|PciPCR_MEM);
- pcicfgw16(pci, PciPCR, r);
-
- /*
- * Treat the found device as an ordinary PCI card.
- * It seems that the CIS is not always present in
- * CardBus cards.
- * XXX, need to support multifunction cards
- */
- for(i = 0; i < Nbars; i++) {
- if(pci->mem[i].size == 0)
- continue;
- bar = pci->mem[i].bar;
- if(bar & 1)
- bar += iobase;
- else
- bar += membase;
- pci->mem[i].bar = bar;
- pcicfgw32(pci, PciBAR0 + 4*i, bar);
- if((bar & 1) == 0){
- print("%T mem[%d] %8.8llux %d\n", pci->tbdf, i, bar, pci->mem[i].size);
- if(bar & 0x80){ /* TO DO: enable prefetch */
- ;
- }
- }
- }
- if((size = pcibarsize(pci, PciEBAR0)) > 0) { /* TO DO: can this be done by
pci.c?  */
- pci->rom.bar = rombase;
- pci->rom.size = size;
- rombase += size;
- pcicfgw32(pci, PciEBAR0, pci->rom.bar);
- }
-
- /* Set the basic PCI registers for the device */
- pci->pcr = pcicfgr16(pci, PciPCR);
- pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master;
- pci->cls = 8;
- pci->ltr = 64;
- pcicfgw16(pci, PciPCR, pci->pcr);
- pcicfgw8(pci, PciCLS, pci->cls);
- pcicfgw8(pci, PciLTR, pci->ltr);
-
- if (pcicfgr8(pci, PciINTP)) {
- pci->intl = pcicfgr8(cb->pci, PciINTL);
- pcicfgw8(pci, PciINTL, pci->intl);
-
- /* Route interrupts to INTA#/B# */
- pcicfgw16(cb->pci, PciBCR,
- pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));
- }
- }
+ pcibusmap(cb->pci->bridge, &membase, &iobase, 1);
 }

 static void


Sun Feb 28 12:06:02 EST 2021
*e820=1 0x0000000000000000 0x000000000008b000 2 0x000000000008b000 0x00000000000
a0000 2 0x00000000000d0000 0x00000000000d4000 2 0x00000000000dc000 0x00000000001
00000 1 0x0000000000100000 0x000000007f6e0000 3 0x000000007f6e0000 0x000000007f6
f5000 4 0x000000007f6f5000 0x000000007f700000 2 0x000000007f700000 0x000000007f8
00000 2 0x000000007f800000 0x0000000080000000 2 0x00000000e0000000 0x00000000f00
00000 2 0x00000000f0008000 0x00000000f000c000 2 0x00000000fec00000 0x00000000fec
10000 2 0x00000000fed14000 0x00000000fed18000 2 0x00000000fed18000 0x00000000fed
19000 2 0x00000000fed19000 0x00000000fed1a000 2 0x00000000fed20000 0x00000000fed
90000 2 0x00000000fee00000 0x00000000fee01000 2 0x00000000ff000000 0x00000001000
00000
monitor=vesa
vgasize=1024x768x16
mouseport=ps2
kbmap=x41t
bootfile=/386/9pc
nobootprompt=tls
nora6=
*nodma=
uart2=type=isa port=0x200 irq=5
ramdisk0=1G
cfs=#S/sdZ0/data
pcmcia0=disabled
*pcihinv=1
boot

Plan 9
126 holes free
0x0001a000 0x0008a000 458752
0x00661000 0x0ffff000 261742592
262201344 bytes free
PCI.0.2.1: bar0: fixed 80000000 524288
PCI.0.31.2: bar0: fixed 00000401 8
PCI.0.31.2: bar1: fixed 00000409 4
PCI.0.31.2: bar2: fixed 00000411 8
PCI.0.31.2: bar3: fixed 0000040D 4
bus dev type vid did intl memory
0 0/0 06 00 00 8086 2590 0
0 2/0 03 00 00 8086 2592 11 0:a0080000 524288 1:00001801 8 2:c0000008 268435456
3:a0000000 262144
0 2/1 03 80 00 8086 2792 0 0:80000000 524288
0 28/0 06 04 00 8086 2660 11 mema:a0100000-a0200000 1048576 ->2
0 29/0 0c 03 00 8086 2658 11 4:00001821 32
0 29/1 0c 03 00 8086 2659 11 4:00001841 32
0 29/2 0c 03 00 8086 265a 11 4:00001861 32
0 29/3 0c 03 00 8086 265b 11 4:00001881 32
0 29/7 0c 03 20 8086 265c 11 0:a0040000 1024
0 30/0 06 04 01 8086 2448 255 ioa:00003000-00007000 16384 mema:a0200000-b0000000
266338304 prefa:d0000000-d8000000 134217728 ->4
0 30/2 04 01 00 8086 266e 11 0:00001c01 256 1:000018c1 64 2:a0040800 512
3:a0040400 256
0 30/3 07 03 00 8086 266d 11 0:00002401 256 1:00002001 128
0 31/0 06 01 00 8086 2641 0
0 31/2 01 01 80 8086 2653 255 0:00000401 8 1:00000409 4 2:00000411 8 3:0000040d 4
4:00001811 16
0 31/3 0c 05 00 8086 266a 11 4:000018a1 32
2 0/0 02 00 00 14e4 167d 11 0:a0100004 65536
4 0/0 06 07 00 1180 0476 11
4 0/1 08 05 00 1180 0822 11 0:a0201000 256
4 2/0 02 80 00 8086 4224 11 0:a0202000 4096
cpu0: 598MHz GenuineIntel P6 (AX 000006D8 CX 00000180 DX AFE9FBFF)
ELCR: 0800
#Y0: Ricoh 476 PCI/Cardbus bridge, A0200000 intl 11
pcienable PCI.5.0.0: pcr 0->2
pcienable PCI.5.0.1: pcr 0->2
pcienable PCI.5.0.2: pcr 0->2
bcm: reset
bcm: 1000 Mbps link, full duplex
#l0: bcm: 1000Mbps port 0xA0100000 irq 11 ea 000ae43dd71a
#A0: ac97 port 0x0000 mixport 0x0000 irq 11
#A0: ac97 warm reset
#A0: ac97 codecs ready: sdin0 sdin1
#A0: ac97 codecs resumed:
#A0: ac97 codec ext: vra
uhci: 0x8086 0x2658: port 0x1820 size 0x20 irq 11
uhci: 0x8086 0x2659: port 0x1840 size 0x20 irq 11
uhci: 0x8086 0x265a: port 0x1860 size 0x20 irq 11
uhci: 0x8086 0x265b: port 0x1880 size 0x20 irq 11
usbohci: 0x1033 0x35: port 80402000 size 0x1000 irq 0
usbohci: 0x1033 0x35: port 80401000 size 0x1000 irq 0
i8259enable: irq -1 out of range
intrenable: couldn't assign irq -1, tbdf 0xC050000 for ohci
i8259enable: irq -1 out of range
intrenable: couldn't assign irq -1, tbdf 0xC050100 for ohci
usbehci: 0x8086 0x265c: port a0040000 size 1024 irq 11
usbehci: 0x1033 0xe0: port 80400000 size 256 irq 0
i8259enable: irq -1 out of range
intrenable: couldn't assign irq -1, tbdf 0xC050200 for ehci
1015M memory: 256M kernel data, 758M user, 1383M swap
setting kbmap to x41t
user[glenda]: james
secstore password:
secstore
dinit: bsize 0x0<= 0
formatting disk
formatting inodes

init: starting /bin/rc


Sun Feb 28 11:51:12 EST 2021
diff -r 4bafb394707a sys/src/9/pc/devpccard.c
--- a/sys/src/9/pc/devpccard.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/pc/devpccard.c Sun Feb 28 17:51:12 2021 +0100
@@ -520,7 +520,6 @@
	static int initialized;
	Pcidev *pci;
	int i;
- uchar intl;
	char *p;

	if (initialized)
@@ -539,9 +538,9 @@

	/* Find all CardBus controllers */
	pci = nil;
- intl = 0xff;
	while ((pci = pcimatch(pci, 0, 0)) != nil) {
		uvlong baddr;
+ int size;
		Cardbus *cb;
		uchar pin;

@@ -633,23 +632,20 @@
			pcicfgw8(cb->pci, 0xD4, 0xCA);
		}

- baddr = pcicfgr32(cb->pci, PciBAR0);
- if (baddr == 0) {
- int size = (pci->did == Ricoh_478_did)?  0x10000: 0x1000;
+ size = (pci->did == Ricoh_478_did)?  0x10000: 0x1000;
+ baddr = (ulong)pcicfgr32(cb->pci, PciBAR0);
+ if (baddr == 0 || upaalloc(baddr, size, 0) == -1) {
			baddr = upaalloc(-1ULL, size, size);
			if(baddr == -1)
				continue;
			pcicfgw32(cb->pci, PciBAR0, (ulong)baddr);
- cb->regs = (ulong *)vmap(baddr, size);
		}
- else
- cb->regs = (ulong *)vmap(baddr, 4096);
+ cb->regs = (ulong *)vmap(baddr, size);
		if(cb->regs == nil)
			continue;
		cb->state = SlotEmpty;

- if (intl != 0xff && intl != pci->intl)
- intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");
+ intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");

		/* Don't really know what to do with this...  */
		i82365probe(cb, LegacyAddr, LegacyAddr + 1);
@@ -777,10 +773,8 @@
 static void
 configure(Cardbus *cb)
 {
- int i, r;
- Pcidev *pci;
- uvlong romlen, memlen, membase, rombase, bar;
- ulong iobase, iolen, size;
+ ulong iobase, iolen;
+ uvlong membase, memlen;

	if(DEBUG)
		print("configuring slot %ld (%s)\n", cb - cbslots,
		states[cb->state]);
@@ -796,23 +790,10 @@
	}

	/* Scan the CardBus for new PCI devices */
- pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge);
+ pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge, cb->pci);

- /*
- * size the devices on the bus, reserve a minimum for devices arriving later,
- * allow for ROM space, allocate space, and set the cardbus mapping registers
- */
- pcibussize(cb->pci->bridge, &memlen, &iolen); /* TO DO: need initial
alignments */
-
- romlen = 0;
- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- size = pcibarsize(pci, PciEBAR0);
- if(size > 0){
- pci->rom.bar = -1;
- pci->rom.size = size;
- romlen += size;
- }
- }
+ /* size the devices on the bus, reserve a minimum for devices arriving later */
+ pcibussize(cb->pci->bridge, &memlen, &iolen);

	if(iolen < 512)
		iolen = 512;
@@ -820,8 +801,6 @@
	if(iobase == -1)
		return;

- rombase = memlen;
- memlen += romlen;
	if(memlen < 1*1024*1024)
		memlen = 1*1024*1024;
	membase = upaalloc(-1ULL, memlen, 4*1024*1024); /* TO DO: better alignment
	*/
@@ -832,68 +811,20 @@
	pcicfgw32(cb->pci, PciCBILR0, iobase + iolen-1);
	pcicfgw32(cb->pci, PciCBIBR1, 0);
	pcicfgw32(cb->pci, PciCBILR1, 0);
+ cb->pci->ioa.bar = iobase;
+ cb->pci->ioa.size = iolen;

	pcicfgw32(cb->pci, PciCBMBR0, (ulong)membase);
	pcicfgw32(cb->pci, PciCBMLR0, (ulong)membase + memlen-1);
	pcicfgw32(cb->pci, PciCBMBR1, 0);
	pcicfgw32(cb->pci, PciCBMLR1, 0);
+ cb->pci->mema.bar = membase;
+ cb->pci->mema.size = memlen;

-// pcibussize(cb->pci->bridge, &membase, &iobase); /* now assign them */
- rombase += membase;
+ /* Route interrupts to INTA#/B# */
+ pcicfgw16(cb->pci, PciBCR, pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));

- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- r = pcicfgr16(pci, PciPCR);
- r &= ~(PciPCR_IO|PciPCR_MEM);
- pcicfgw16(pci, PciPCR, r);
-
- /*
- * Treat the found device as an ordinary PCI card.
- * It seems that the CIS is not always present in
- * CardBus cards.
- * XXX, need to support multifunction cards
- */
- for(i = 0; i < Nbars; i++) {
- if(pci->mem[i].size == 0)
- continue;
- bar = pci->mem[i].bar;
- if(bar & 1)
- bar += iobase;
- else
- bar += membase;
- pci->mem[i].bar = bar;
- pcicfgw32(pci, PciBAR0 + 4*i, bar);
- if((bar & 1) == 0){
- print("%T mem[%d] %8.8llux %d\n", pci->tbdf, i, bar, pci->mem[i].size);
- if(bar & 0x80){ /* TO DO: enable prefetch */
- ;
- }
- }
- }
- if((size = pcibarsize(pci, PciEBAR0)) > 0) { /* TO DO: can this be done by
pci.c?  */
- pci->rom.bar = rombase;
- pci->rom.size = size;
- rombase += size;
- pcicfgw32(pci, PciEBAR0, pci->rom.bar);
- }
-
- /* Set the basic PCI registers for the device */
- pci->pcr = pcicfgr16(pci, PciPCR);
- pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master;
- pci->cls = 8;
- pci->ltr = 64;
- pcicfgw16(pci, PciPCR, pci->pcr);
- pcicfgw8(pci, PciCLS, pci->cls);
- pcicfgw8(pci, PciLTR, pci->ltr);
-
- if (pcicfgr8(pci, PciINTP)) {
- pci->intl = pcicfgr8(cb->pci, PciINTL);
- pcicfgw8(pci, PciINTL, pci->intl);
-
- /* Route interrupts to INTA#/B# */
- pcicfgw16(cb->pci, PciBCR,
- pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));
- }
- }
+ pcibusmap(cb->pci->bridge, &membase, &iobase, 1);
 }

 static void
diff -r 4bafb394707a sys/src/9/pc/mp.c
--- a/sys/src/9/pc/mp.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/pc/mp.c Sun Feb 28 17:51:12 2021 +0100
@@ -351,13 +351,19 @@

	if(bus == nil){
		/*
- * if the PCI device is behind a PCI-PCI bridge thats not described
- * by the MP or ACPI tables then walk up the bus translating interrupt
- * pin to parent bus.
+ * if the PCI device is behind a bridge thats not described
+ * by the MP or ACPI tables then walk up the bus translating
+ * interrupt pin to parent bus.
		 */
		if(pci != nil && pci->parent != nil && pin > 0){
- pin = ((dno+(pin-1))%4)+1;
			pci = pci->parent;
+ if(pci->ccrb == 6 && pci->ccru == 7){
+ /* Cardbus bridge, use controllers interrupt pin */
+ pin = pcicfgr8(pci, PciINTP);
+ } else {
+ /* PCI-PCI bridge */
+ pin = ((dno+(pin-1))%4)+1;
+ }
			bno = BUSBNO(pci->tbdf);
			dno = BUSDNO(pci->tbdf);
			goto Findbus;
diff -r 4bafb394707a sys/src/9/pc/pcipc.c
--- a/sys/src/9/pc/pcipc.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/pc/pcipc.c Sun Feb 28 17:51:12 2021 +0100
@@ -688,7 +688,7 @@
	list = &pciroot;
	for(bno = 0; bno <= pcimaxbno; bno++) {
		int sbno = bno;
- bno = pciscan(bno, list);
+ bno = pciscan(bno, list, nil);

		while(*list)
			list = &(*list)->link;
diff -r 4bafb394707a sys/src/9/port/pci.c
--- a/sys/src/9/port/pci.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/port/pci.c Sun Feb 28 17:51:12 2021 +0100
@@ -643,9 +643,9 @@
 }

 int
-pciscan(int bno, Pcidev **list)
+pciscan(int bno, Pcidev **list, Pcidev *parent)
 {
- return pcilscan(bno, list, nil);
+ return pcilscan(bno, list, parent);
 }

 void
diff -r 4bafb394707a sys/src/9/port/pci.h
--- a/sys/src/9/port/pci.h Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/port/pci.h Sun Feb 28 17:51:12 2021 +0100
@@ -228,7 +228,7 @@
 extern int pcicfgr8(Pcidev* pcidev, int rno);
 extern void pcicfgw8(Pcidev* pcidev, int rno, int data);

-extern int pciscan(int bno, Pcidev **list);
+extern int pciscan(int bno, Pcidev **list, Pcidev *parent);
 extern void pcibusmap(Pcidev *root, uvlong *pmema, ulong *pioa, int wrreg);
 extern void pcibussize(Pcidev *root, uvlong *msize, ulong *iosize);



Sun Feb 28 11:49:52 EST 2021
diff -r 4bafb394707a sys/src/9/pc/devpccard.c
--- a/sys/src/9/pc/devpccard.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/pc/devpccard.c Sun Feb 28 17:49:51 2021 +0100
@@ -520,7 +520,6 @@
	static int initialized;
	Pcidev *pci;
	int i;
- uchar intl;
	char *p;

	if (initialized)
@@ -539,9 +538,9 @@

	/* Find all CardBus controllers */
	pci = nil;
- intl = 0xff;
	while ((pci = pcimatch(pci, 0, 0)) != nil) {
		uvlong baddr;
+ int size;
		Cardbus *cb;
		uchar pin;

@@ -633,23 +632,20 @@
			pcicfgw8(cb->pci, 0xD4, 0xCA);
		}

- baddr = pcicfgr32(cb->pci, PciBAR0);
- if (baddr == 0) {
- int size = (pci->did == Ricoh_478_did)?  0x10000: 0x1000;
+ size = (pci->did == Ricoh_478_did)?  0x10000: 0x1000;
+ baddr = (ulong)pcicfgr32(cb->pci, PciBAR0);
+ if (baddr == 0 || upaalloc(baddr, size, 0) == -1) {
			baddr = upaalloc(-1ULL, size, size);
			if(baddr == -1)
				continue;
			pcicfgw32(cb->pci, PciBAR0, (ulong)baddr);
- cb->regs = (ulong *)vmap(baddr, size);
		}
- else
- cb->regs = (ulong *)vmap(baddr, 4096);
+ cb->regs = (ulong *)vmap(baddr, size);
		if(cb->regs == nil)
			continue;
		cb->state = SlotEmpty;

- if (intl != 0xff && intl != pci->intl)
- intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");
+ intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");

		/* Don't really know what to do with this...  */
		i82365probe(cb, LegacyAddr, LegacyAddr + 1);
@@ -778,9 +774,8 @@
 configure(Cardbus *cb)
 {
	int i, r;
- Pcidev *pci;
- uvlong romlen, memlen, membase, rombase, bar;
- ulong iobase, iolen, size;
+ ulong iobase, iolen;
+ uvlong membase, memlen;

	if(DEBUG)
		print("configuring slot %ld (%s)\n", cb - cbslots,
		states[cb->state]);
@@ -796,23 +791,10 @@
	}

	/* Scan the CardBus for new PCI devices */
- pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge);
+ pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge, cp->pci);

- /*
- * size the devices on the bus, reserve a minimum for devices arriving later,
- * allow for ROM space, allocate space, and set the cardbus mapping registers
- */
- pcibussize(cb->pci->bridge, &memlen, &iolen); /* TO DO: need initial
alignments */
-
- romlen = 0;
- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- size = pcibarsize(pci, PciEBAR0);
- if(size > 0){
- pci->rom.bar = -1;
- pci->rom.size = size;
- romlen += size;
- }
- }
+ /* size the devices on the bus, reserve a minimum for devices arriving later */
+ pcibussize(cb->pci->bridge, &memlen, &iolen);

	if(iolen < 512)
		iolen = 512;
@@ -820,8 +802,6 @@
	if(iobase == -1)
		return;

- rombase = memlen;
- memlen += romlen;
	if(memlen < 1*1024*1024)
		memlen = 1*1024*1024;
	membase = upaalloc(-1ULL, memlen, 4*1024*1024); /* TO DO: better alignment
	*/
@@ -832,68 +812,20 @@
	pcicfgw32(cb->pci, PciCBILR0, iobase + iolen-1);
	pcicfgw32(cb->pci, PciCBIBR1, 0);
	pcicfgw32(cb->pci, PciCBILR1, 0);
+ cb->pci->ioa.bar = iobase;
+ cp->pci->ioa.siz = iolen;

	pcicfgw32(cb->pci, PciCBMBR0, (ulong)membase);
	pcicfgw32(cb->pci, PciCBMLR0, (ulong)membase + memlen-1);
	pcicfgw32(cb->pci, PciCBMBR1, 0);
	pcicfgw32(cb->pci, PciCBMLR1, 0);
+ cp->pci->mema.bar = membase;
+ cb->pci->mema.siz = memlen;

-// pcibussize(cb->pci->bridge, &membase, &iobase); /* now assign them */
- rombase += membase;
+ /* Route interrupts to INTA#/B# */
+ pcicfgw16(cb->pci, PciBCR, pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));

- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- r = pcicfgr16(pci, PciPCR);
- r &= ~(PciPCR_IO|PciPCR_MEM);
- pcicfgw16(pci, PciPCR, r);
-
- /*
- * Treat the found device as an ordinary PCI card.
- * It seems that the CIS is not always present in
- * CardBus cards.
- * XXX, need to support multifunction cards
- */
- for(i = 0; i < Nbars; i++) {
- if(pci->mem[i].size == 0)
- continue;
- bar = pci->mem[i].bar;
- if(bar & 1)
- bar += iobase;
- else
- bar += membase;
- pci->mem[i].bar = bar;
- pcicfgw32(pci, PciBAR0 + 4*i, bar);
- if((bar & 1) == 0){
- print("%T mem[%d] %8.8llux %d\n", pci->tbdf, i, bar, pci->mem[i].size);
- if(bar & 0x80){ /* TO DO: enable prefetch */
- ;
- }
- }
- }
- if((size = pcibarsize(pci, PciEBAR0)) > 0) { /* TO DO: can this be done by
pci.c?  */
- pci->rom.bar = rombase;
- pci->rom.size = size;
- rombase += size;
- pcicfgw32(pci, PciEBAR0, pci->rom.bar);
- }
-
- /* Set the basic PCI registers for the device */
- pci->pcr = pcicfgr16(pci, PciPCR);
- pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master;
- pci->cls = 8;
- pci->ltr = 64;
- pcicfgw16(pci, PciPCR, pci->pcr);
- pcicfgw8(pci, PciCLS, pci->cls);
- pcicfgw8(pci, PciLTR, pci->ltr);
-
- if (pcicfgr8(pci, PciINTP)) {
- pci->intl = pcicfgr8(cb->pci, PciINTL);
- pcicfgw8(pci, PciINTL, pci->intl);
-
- /* Route interrupts to INTA#/B# */
- pcicfgw16(cb->pci, PciBCR,
- pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));
- }
- }
+ pcibusmap(cb->pci->bridge, &membase, &iobase, 1);
 }

 static void
diff -r 4bafb394707a sys/src/9/pc/mp.c
--- a/sys/src/9/pc/mp.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/pc/mp.c Sun Feb 28 17:49:51 2021 +0100
@@ -351,13 +351,19 @@

	if(bus == nil){
		/*
- * if the PCI device is behind a PCI-PCI bridge thats not described
- * by the MP or ACPI tables then walk up the bus translating interrupt
- * pin to parent bus.
+ * if the PCI device is behind a bridge thats not described
+ * by the MP or ACPI tables then walk up the bus translating
+ * interrupt pin to parent bus.
		 */
		if(pci != nil && pci->parent != nil && pin > 0){
- pin = ((dno+(pin-1))%4)+1;
			pci = pci->parent;
+ if(pci->ccrb == 6 && pci->ccru == 7){
+ /* Cardbus bridge, use controllers interrupt pin */
+ pin = pcicfgr8(pci, PciINTP);
+ } else {
+ /* PCI-PCI bridge */
+ pin = ((dno+(pin-1))%4)+1;
+ }
			bno = BUSBNO(pci->tbdf);
			dno = BUSDNO(pci->tbdf);
			goto Findbus;
diff -r 4bafb394707a sys/src/9/pc/pcipc.c
--- a/sys/src/9/pc/pcipc.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/pc/pcipc.c Sun Feb 28 17:49:51 2021 +0100
@@ -688,7 +688,7 @@
	list = &pciroot;
	for(bno = 0; bno <= pcimaxbno; bno++) {
		int sbno = bno;
- bno = pciscan(bno, list);
+ bno = pciscan(bno, list, nil);

		while(*list)
			list = &(*list)->link;
diff -r 4bafb394707a sys/src/9/port/pci.c
--- a/sys/src/9/port/pci.c Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/port/pci.c Sun Feb 28 17:49:51 2021 +0100
@@ -643,9 +643,9 @@
 }

 int
-pciscan(int bno, Pcidev **list)
+pciscan(int bno, Pcidev **list, Pcidev *parent)
 {
- return pcilscan(bno, list, nil);
+ return pcilscan(bno, list, parent);
 }

 void
diff -r 4bafb394707a sys/src/9/port/pci.h
--- a/sys/src/9/port/pci.h Sun Feb 28 13:31:49 2021 +0100
+++ b/sys/src/9/port/pci.h Sun Feb 28 17:49:51 2021 +0100
@@ -228,7 +228,7 @@
 extern int pcicfgr8(Pcidev* pcidev, int rno);
 extern void pcicfgw8(Pcidev* pcidev, int rno, int data);

-extern int pciscan(int bno, Pcidev **list);
+extern int pciscan(int bno, Pcidev **list, Pcidev *parent);
 extern void pcibusmap(Pcidev *root, uvlong *pmema, ulong *pioa, int wrreg);
 extern void pcibussize(Pcidev *root, uvlong *msize, ulong *iosize);



Sun Feb 28 11:21:00 EST 2021
Winter gifts for you - https://redirect.7offers.ru/e36bfc98

Sun Feb 28 10:55:11 EST 2021
0.0.0: brg 06.00.00 8086/2590 0
	Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM
	Controller
0.2.0: vid 03.00.00 8086/2592 11 0:a0080000 524288 1:00001801 8 2:c0000008
268435456 3:a0000000 262144
	Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller
0.2.1: vid 03.80.00 8086/2792 0 0:80000000 524288
	Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller
0.28.0: brg 06.04.00 8086/2660 11
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1
0.29.0: usb 0c.03.00 8086/2658 11 4:00001821 32
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1
0.29.1: usb 0c.03.00 8086/2659 11 4:00001841 32
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2
0.29.2: usb 0c.03.00 8086/265a 11 4:00001861 32
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3
0.29.3: usb 0c.03.00 8086/265b 11 4:00001881 32
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4
0.29.7: usb 0c.03.20 8086/265c 11 0:a0040000 1024
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller
0.30.0: brg 06.04.01 8086/2448 255
	Intel Corporation 82801 Mobile PCI Bridge
0.30.2: aud 04.01.00 8086/266e 11 0:00001c01 256 1:000018c1 64 2:a0040800 512
3:a0040400 256
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio
	Controller
0.30.3: ser 07.03.00 8086/266d 11 0:00002401 256 1:00002001 128
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem
	Controller
0.31.0: brg 06.01.00 8086/2641 0
	Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge
0.31.2: disk 01.01.80 8086/2653 255 0:00000401 8 1:00000409 4 2:00000411 8
3:0000040d 4 4:00001811 16
	Intel Corporation 82801FBM (ICH6M) SATA Controller
0.31.3: smb 0c.05.00 8086/266a 11 4:000018a1 32
	Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller
2.0.0: net 02.00.00 14e4/167d 11 0:a0100004 65536
	Broadcom Inc.  and subsidiaries NetXtreme BCM5751M Gigabit Ethernet PCI
	Express
4.0.0: brg 06.07.00 1180/0476 11
	Ricoh Co Ltd RL5c476 II
4.0.1: base 08.05.00 1180/0822 11 0:a0201000 256
	Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter
4.2.0: net 02.80.00 8086/4224 11 0:a0202000 4096
	Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection
5.0.0: usb 0c.03.10 1033/0035 11 0:80400000 4096
	NEC Corporation OHCI USB Controller
5.0.1: usb 0c.03.10 1033/0035 11 0:80400000 4096
	NEC Corporation OHCI USB Controller
5.0.2: usb 0c.03.20 1033/00e0 11 0:80400000 256
	NEC Corporation uPD72010x USB 2.0 Controller


Sun Feb 28 10:45:05 EST 2021
0000000 80 11 76 04 07 01 10 02 8d 00 07 06 00 40 82 00
0000010 00 00 20 a0 dc 00 00 22 04 05 07 b0 00 00 40 80
0000020 00 f0 4f 80 00 00 00 00 00 00 00 00 18 04 00 00
0000030 14 06 00 00 00 00 00 00 00 00 00 00 0b 01 00 07
0000040 14 10 55 05 e1 03 00 00 00 00 00 00 00 00 00 00
0000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000080 01 00 80 04 00 00 00 00 64 04 63 04 01 00 00 00
0000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000a0 00 00 0a 00 00 00 00 00 00 00 30 00 00 00 00 00
00000b0 00 00 00 00 00 00 00 f6 00 38 00 00 00 00 00 00
00000c0 14 10 55 05 00 00 00 00 00 00 00 00 00 00 00 00
00000d0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 0a fe
00000e0 00 c0 c0 24 00 00 00 00 00 00 00 00 00 00 00 00
00000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000100
0000100


Sun Feb 28 10:41:28 EST 2021
0000000 33 10 e0 00 06 00 10 02 04 20 03 0c 08 40 00 00
0000010 00 00 40 80 00 00 00 00 00 00 00 00 00 00 00 00
0000020 00 00 00 00 00 00 00 00 00 00 00 00 35 17 e0 00
0000030 00 00 00 00 40 00 00 00 00 00 00 00 0b 03 10 22
0000040 01 00 02 7e 00 00 00 00 00 00 00 00 00 00 00 00
0000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000060 20 20 3f 00 00 00 00 00 00 00 00 00 00 00 00 00
0000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000e0 05 33 b0 c4 00 00 00 00 01 00 00 00 00 00 00 c0
00000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000100
0000100


Sun Feb 28 10:40:59 EST 2021
0000000 33 10 35 00 06 00 10 02 43 10 03 0c 08 40 00 00
0000010 00 00 40 80 00 00 00 00 00 00 00 00 00 00 00 00
0000020 00 00 00 00 00 00 00 00 00 00 00 00 33 10 33 10
0000030 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 01 2a
0000040 01 00 02 7e 00 00 00 00 00 00 00 00 00 00 00 00
0000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000100
0000100


Sun Feb 28 10:40:43 EST 2021
0000000 33 10 35 00 06 00 10 02 43 10 03 0c 08 40 80 00
0000010 00 00 40 80 00 00 00 00 00 00 00 00 00 00 00 00
0000020 00 00 00 00 00 00 00 00 00 00 00 00 33 10 35 17
0000030 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 01 2a
0000040 01 00 02 7e 00 00 00 00 00 00 00 00 00 00 00 00
0000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000e0 05 33 b0 c4 00 00 00 00 00 00 00 00 00 00 00 00
00000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000100
0000100


Sun Feb 28 10:33:34 EST 2021
diff -r b2bea92dffd4 sys/src/9/pc/mp.c
--- a/sys/src/9/pc/mp.c Sat Feb 20 21:02:07 2021 -0800
+++ b/sys/src/9/pc/mp.c Sun Feb 28 15:33:34 2021 +0000
@@ -351,13 +351,20 @@

	if(bus == nil){
		/*
- * if the PCI device is behind a PCI-PCI bridge thats not described
- * by the MP or ACPI tables then walk up the bus translating interrupt
- * pin to parent bus.
+ * if the PCI device is behind a bridge thats not described
+ * by the MP or ACPI tables then walk up the bus translating
+ * interrupt pin to parent bus.
		 */
+ if(pci->ccrb == 6 && pci->ccru == 7){
+ /* Cardbus bridge, use controllers interrupt pin */
+ pin = pcicfgr8(pci, PciINTP);
+ }
		if(pci != nil && pci->parent != nil && pin > 0){
- pin = ((dno+(pin-1))%4)+1;
			pci = pci->parent;
+ if(pci->ccrb != 6 && pci->ccru != 7) {
+ /* PCI-PCI bridge */
+ pin = ((dno+(pin-1))%4)+1;
+ }
			bno = BUSBNO(pci->tbdf);
			dno = BUSDNO(pci->tbdf);
			goto Findbus;


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